Running documentation scripts on the top directory shifted all links one
level dowwn and is breaking all incoming links.
Use a script to copy all RST files into the doc/ directory before
running sphinx and keep structure intact.
Jira: ZEP-1579
Change-Id: Iccff068430e2ddb29e172cd8ae920475815d199e
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Remove the convert_to_double function and use sensor_value_to_double
from sensor.h.
Change-Id: I92ef4219057f431917f4c8e9d46d4ee2074b423b
Signed-off-by: Bogdan Davidoaia <bogdan.davidoaia@linaro.org>
Remove the type field from the sensor value structure. All values will
have the type previously defined by SENSOR_VALUE_TYPE_INT_PLUS_MICRO.
This simplifies the interface, as apps will know what value type to
expect. Apps that prefer to use double values can optain them using the
sensor_value_to_double function.
Change-Id: I3588d74258030eb16c3f89d8eead13cca4606b18
Signed-off-by: Bogdan Davidoaia <bogdan.davidoaia@linaro.org>
Similar to what was available with nano timers in the original kernel,
allow a user to associate opaque data with a timer.
Fix for ZEP-1558.
Change-Id: Ib8cf998b47988da27eba4ee5cd2658f90366b1e4
Signed-off-by: Benjamin Walsh <walsh.benj@gmail.com>
Added TICK_IRQ definition for CONFIG_PULPINO_TIMER and
CONFIG_RISCV_QEMU_TIMER
skip definition of HAS_POWERSAVE_INSTRUCTION for
CONFIG_SOC_RISCV32_QEMU, since it does not provide
power saving instruction.
Otherwise, not passing sanitycheck.
Change-Id: I2faa823226cd76d129d2bc3db961c9b862aaf784
Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
Added TICK_IRQ definition for CONFIG_PULPINO_TIMER and
CONFIG_RISCV_QEMU_TIMER
skip definition of HAS_POWERSAVE_INSTRUCTION for
CONFIG_SOC_RISCV32_QEMU, since it does not provide
power saving instruction.
Otherwise, not passing sanitycheck.
Change-Id: I43a5c5112d694efdc14c5a0bcb4cafdc196d2680
Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
zedboard_pulpino
1) has a 16750 uart, which is compatible with the uart_ns16550 driver.
2) make use of the pulpino timer driver
Change-Id: Ifda710fc8dea547ada05bb42e604d7cfdff284d5
Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
The qemu_riscv32 board makes use of:
1) the uart_riscv_qemu driver
2) the riscv_qemu_timer driver
Change-Id: I413e3990a66bc62a0d15d82ebca6940b381fed43
Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
tested with blinky, button and disco apps
Change-Id: I4b520d4f3e42c97e4a723747ce4a6c67ca9f1d18
Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
added USED_RAM_SIZE and MAX_HEAP_SIZE definitions for
SOC_RISCV32_QEMU and SOC_RISCV32_PULPINO.
Otherwise, not passing sanitycheck
Change-Id: Ia32b12e1694dc472e9f7f9eb10c5f2e12e928c3a
Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
riscv-qemu UART:
1) comprises only one register that is used to send or
receive characters in a polling fashion.
2) does not have a FIFO and is not interrupt-driven.
Change-Id: I9408f1776eba4cec4aa203a5da759ec04bcddf1f
Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
The riscv-qemu timer driver does not implement
TICKLESS_IDLE
Change-Id: I3eeb5abb05b3f16b55ab9343c2045295b3010cfd
Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
The pulpino_timer driver does not implement TICKLESS_IDLE
for the time being.
Change-Id: I0cce8c8a7e203d551a924863462e6c86af4c98ff
Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
pulpino soc has custom-extended riscv ISA that is accounted
for if CONFIG_RISCV_GENERIC_TOOLCHAIN is not set.
(ex: bit manipulation asm opcodes)
Change-Id: I4dafc4ebc2fedcc4eb6a3dedd0412816afea6004
Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
Default 256 bytes stack size for idle task is not enough, as
stack grows/shrinks by a multiple of 16-bytes in the
RISC-V architecture.
Increase it to 512 bytes for RISCV32 architecture
Change-Id: I8321c48e4c1a877b252ba5561f3cbdd1fe475fc7
Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
added _MOVE_INSTR for RISCV32 architecture
The store instruction has a different syntax in RISC-V,
compared to the other architectures. Hence, for each
architecture, specify the entire load instruction within
the _MOVE_INSTR variable.
Change-Id: Iedc421e73411876abd8b698f7d4b46081b473d79
Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
RISC-V is an open-source instruction set architecture.
Added support for the 32bit version of RISC-V to Zephyr.
1) exceptions/interrupts/faults are handled at the architecture
level via the __irq_wrapper handler. Context saving/restoring
of registers can be handled at both architecture and SOC levels.
If SOC-specific registers need to be saved, SOC level needs to
provide __soc_save_context and __soc_restore_context functions
that shall be accounted by the architecture level, when
corresponding config variable RISCV_SOC_CONTEXT_SAVE is set.
2) As RISC-V architecture does not provide a clear ISA specification
about interrupt handling, each RISC-V SOC handles it in its own
way. Hence, at the architecture level, the __irq_wrapper handler
expects the following functions to be provided by the SOC level:
__soc_is_irq: to check if the exception is the result of an
interrupt or not.
__soc_handle_irq: handle pending IRQ at SOC level (ex: clear
pending IRQ in SOC-specific IRQ register)
3) Thread/task scheduling, as well as IRQ offloading are handled via
the RISC-V system call ("ecall"), which is also handled via the
__irq_wrapper handler. The _Swap asm function just calls "ecall"
to generate an exception.
4) As there is no conventional way of handling CPU power save in
RISC-V, the default nano_cpu_idle and nano_cpu_atomic_idle
functions just unlock interrupts and return to the caller, without
issuing any CPU power saving instruction. Nonetheless, to allow
SOC-level to implement proper CPU power save, nano_cpu_idle and
nano_cpu_atomic_idle functions are defined as __weak
at the architecture level.
Change-Id: I980a161d0009f3f404ad22b226a6229fbb492389
Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
Compiling Zephyr with an external riscv32 toolchain would
require the following env variables to be exported:
export ZEPHYR_GCC_VARIANT=riscv32
export RISCV32_TOOLCHAIN_PATH=/PATH/TO/TOOLCHAIN/BINARY
Change-Id: I2072ed9079a4cabd27837ab39b947bc0a0a1a8b4
Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
Be nice and inform user about unsupported and dropped frames.
Change-Id: Iaf0e7ed660a926c45dac9fc36b788c4c786eac11
Signed-off-by: Johann Fischer <j.fischer@phytec.de>
This makes it possible to setup a Bluetooth connection using net_bt shell
commands.
Change-Id: Ie4ae7e61345315ef987a00b6b5a28c0419f6b1c8
Signed-off-by: Luiz Augusto von Dentz <luiz.von.dentz@intel.com>
This adds NET_REQUEST_BT_DISCONNECT which can be used to disconnect
IPSP in case it is connected.
Change-Id: I8da00b02ee08611bef5f4c0708936b2d31fd2a93
Signed-off-by: Luiz Augusto von Dentz <luiz.von.dentz@intel.com>
This adds NET_REQUEST_BT_SCAN which can be used to scan peripherals
advertising IPSS UUID.
Change-Id: I2463079d182b4da080e6ef94d883c7c1e24a454c
Signed-off-by: Luiz Augusto von Dentz <luiz.von.dentz@intel.com>
This adds a shell module called "net_bt" that exposes Bluetooth L2
management commands.
Change-Id: Ia6da1d38cfd51502119758a8f6abbb6d1cd31743
Signed-off-by: Luiz Augusto von Dentz <luiz.von.dentz@intel.com>
Connect command can be used to initiate a connection, which in IPSP
terminology refer to a router role.
Change-Id: I12b9428924c88a9c68d3adbfe9016a0dd690aade
Signed-off-by: Luiz Augusto von Dentz <luiz.von.dentz@intel.com>
Including logging/sys_log.h before net_core.h prevents SYS_LOG_LEVEL,
etc, to be set properly.
Change-Id: Iaa7aa98110aa455162836be1d9560fbfc03569df
Signed-off-by: Luiz Augusto von Dentz <luiz.von.dentz@intel.com>
If the interface is not UP wait for MGMT event if that is enabled.
Change-Id: I4866c23d1e6f5b1a7cf212434d794673d7e756ce
Signed-off-by: Luiz Augusto von Dentz <luiz.von.dentz@intel.com>
CONFIG_NETWORKING_WITH_BT no longer exist, instead
CONFIG_NET_L2_BLUETOOTH shall be used.
Change-Id: Ide353b7620228e431c535768b37749994caf8e8b
Signed-off-by: Luiz Augusto von Dentz <luiz.von.dentz@intel.com>
This decodes the event layer, code and type when debugging is enabled.
Change-Id: I23c6fb200f3287a138e46df9f472c9982898675d
Signed-off-by: Luiz Augusto von Dentz <luiz.von.dentz@intel.com>
They should return the same value as in NET_MGMT_LAYER and
NET_MGMT_LAYER_CODE.
Change-Id: Ia95adcd3b6b6aaf0ed29f3260bc54784ca532d8f
Signed-off-by: Luiz Augusto von Dentz <luiz.von.dentz@intel.com>
It was missing for arduino_101.
Jira: ZEP-1574
Change-Id: I08fc0961b94f5f7b1b787ebf52e7d9922e38006c
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
When CONFIG_NET_MGMT_EVENT is not set, it will still be able to compile
code using net_mgmt_event related functions.
Change-Id: I6824c57093636867ea4228338aa6c02913975510
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
net_context_put() forgot to release the conn_handler field causing
subsequent failures in net_conn_register() when they ran out.
Change-Id: I0d306b5035199422fa8788338ac9da8d1900d5f9
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
TCP didn't actually have a way to signal synchronous receipt of a FIN
packet. Extend the recv_cb API to allow a NULL buf argument with
status==0 (by analogy to Unix's zero-length read) to signal EOF.
Update docs too, and also echo_server which wasn't prepared to handle
this situation.
Change-Id: I7dc08f9e262a81dcad9c670c6471898889f0b05d
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Anas Nashif