This patch corrects gpio_dw_setup to use the MMIO base address
determined by PCI enumeration when that enumeration feature is enabled
instead of always using the default base address specified at compile
time.
Change-Id: If139c40ce30275694e01196a4a4aa529cd714f06
Signed-off-by: Michael LeMay <michael.lemay@intel.com>
Change-Id: I34a54230bc4a63c8a4391d03ff530835910c3705
Signed-off-by: Dan Kalowsky <daniel.kalowsky@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
In order to have drivers that are usable cross architecture the
signature for IRQ_CONFIG needs to be the same to avoid #ifdef hell in
the driver code based on architecture.
Update the macro and it usage for existing drivers
Change-Id: I22e142b21d4e984add231d1dbd97020e4823985f
Signed-off-by: Dirk Brandewie <dirk.j.brandewie@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
The naming convention used in the source is for there to be an
_ and not a - in the file. Fixing GPIO to be consistent with
the os naming conventions.
Change-Id: Ifc4356c14b52e2cc2411a7445b44c7cb57d2765c
Signed-off-by: Dan Kalowsky <daniel.kalowsky@intel.com>
Gets rid of the trailing initialization level character from the
name of the device variable generated by the macro, since it serves
no useful purpose. (The linker scripts place the various initialization
sections in ascending order based on the name of the section, so there
is no need to embed the initialization level in the variable name itself.)
Change-Id: I56bb79a513b8f77fb1f3fbaccec14454c2520772
Signed-off-by: Allan Stephens <allan.stephens@windriver.com>
Change all the Intel and Wind River code license from BSD-3 to Apache 2.
Change-Id: Id8be2c1c161a06ea8a0b9f38e17660e11dbb384b
Signed-off-by: Javier B Perez Hernandez <javier.b.perez.hernandez@linux.intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Signed-off-by: Allan Stephens <allan.stephens@windriver.com>
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
The newly introduced i2c_poll_transfer() is now used for register
read for PCAL9535A GPIO driver. The old write then read does not
work because every read or write ends with STOP. However,
the chip requires RESTART after writing the register address.
So the new generic transfer function is perfect for this.
Change-Id: I56d7ebe08f68cb04731c72138d60645ef124f65e
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
If using with shared IRQ, this function will be called by
the shared IRQ driver. So we need to check and bail out
early if the interrupt is not coming from the GPIO
controller.
Change-Id: I4ae925f5fb9a5c32d03a180edc8460e978ec0aac
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Handle only the pins which have been configured to be present on this
controller. Removing an unused #define as well.
Change-Id: I66d3638333f1fcd49b1b4f70a5c9d11dbc538fd0
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
On some platforms (e.g. Galileo), the GPIO controller is on PCI bus,
which shares IRQ with other devices (I2C on Galileo). This patch
adds support for utilizing shared IRQ.
Change-Id: I4b44bae15356e4710d54f0343fed1bd27f35e484
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The polling I2C write function guarantees the write operation
is completed. Given that the initialization routine goes through
I2C write consecutively, we want to make sure each write
has been committed.
Also adds code to configure the I2C controller before transfer.
Change-Id: I2c8888e940edd1cb9fb01f03234a731ac991dfcf
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Add I/O port access to MMIO-based GPIO driver, in addition to
the existing direct memory access. This extends the driver,
so that it can address the registers through I/O read/write.
Change-Id: I53c74ad76472ac043764e33bfbb77a2bedc427fe
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Add a Kconfig option to enable NANO_TIMERS for PCAL9535A.
Without enabling nano timers, compilation may fail.
Change-Id: If96358a17b9522f9323f3480b4716c3dfd82a3de
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
There are devices that need are part of the architecture core the need
to be initialized prior to devices that are integrated around a core
to make up a complete SOC. Namely the interrupt controller in the SOC
must be configured in order to allow the integrated IP blocks drivers
to initialize correctly.
Change-Id: I0a91e08f98516a7b7dd402ffc6494a071f1326b2
Signed-off-by: Dirk Brandewie <dirk.j.brandewie@intel.com>
This macro is legacy from an early implementation of the init system
before the pure level was split into early and late phases remove it
now to avoid confusion going forward.
Change-Id: I6720874c840c9e14888fd6f411a8182e7420ca29
Signed-off-by: Dirk Brandewie <dirk.j.brandewie@intel.com>
Fixes a build failure in designware gpio driver.
Change-Id: I90a540f56bff17ff56d0315356fde6d6c4d02407
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Register values are now being cached in memory, and are being used in
subsequent writes. This is to avoid reading from registers, as
we know what needs to be written to those registers all the time.
Change-Id: I9b344303c0cb9f28e974514ab674135004f68ea0
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The _has_i2c_master() should return 1 if there is an I2C master.
The logic was incorrectly inverted. So fix it now.
Change-Id: Ic4bf44efc1f68644530a275f0c4e454740a2950a
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This adds a simple driver for MMIO-based GPIO ports.
It does not trigger any interrupts due to pin level at this moment.
Change-Id: I0c439f221988817e4be72653c68257ef6ace5bde
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This adds the driver for I2C-based PCAL9535A GPIO chip.
This currently only enables minimal set of features of the chip for
very simple input/output operations, and does not support interrupt
yet.
Change-Id: I32ea07a71a38866280a96e68cff49cb0df12b85d
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This change puts the DW GPIO Kconfig selections inside GPIO menu.
This also groups all DW GPIO related selections under GPIO_DW.
Change-Id: I776f3f6b89e1a4dc366648f8290abb27de9eceb8
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The code fragment to bind the instances of the GPIO driver were being
replicated in every platform_config.c This code is not platform
specific but is driver specific.
All the information required to bind a driver instance comes from
CONFIG_ variables. Having the binding code with the driver code
avoids duplicating the code fragments in each platform where the
driver may be used.
Change-Id: Ie07a3d12d25201e82ce7074455e6c036f463851b
Signed-off-by: Dirk Brandewie <dirk.j.brandewie@intel.com>
When configured as GPIO_ACCESS_BY_PIN, the callback should
be called only if the pin is enabled and received an interrupt.
Change-Id: I7addeb57c8d46dddc027e9b82a92654cd210ade1
Signed-off-by: Ricardo de Almeida Gonzaga <ricardo.gonzaga@intel.com>
- Device ID was wrong
- Setting default class id
Change-Id: I9fd1df284eca4067c21beffa7599307a40be5144
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
A fix for a mistake introduced in commit 1a7357.
Change-Id: I411937c85f29abb934ae5385f4858950f5d76887
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
This will enable the possibility to use this driver with Quark X1000.
Change-Id: Ic40b750d608488e97cc7662cad6c6d66dbf428ab
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Just to align the code to generic memory mapped registers and bit
operations functions.
Change-Id: I0fe8b3b6687670d0ed0daffe52645ec2c6b4c674
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
This commit fixes the set bit function.
If the value to set is different from zero, then
the indicated bit will be set.
Change-Id: I9c42f683d108b371ca821f446ac5a10541b89b9f
Signed-off-by: Juan Manuel Cruz <juan.m.cruz.alcaraz@linux.intel.com>
[DL: captilize commit message title; fixed some whitespaces;
changed the __initconfig_gpio_* from level 0 to level 1,
which is the level of pure_init; and added include path
to board.h; ]
Change-Id: I7eea6a6ca9e4b7cf8d1ccabb57f07f786da93ef0
Signed-off-by: Dirk Brandewie <dirk.j.brandewie@intel.com>
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Michael LeMay