When operating on different kinds of heaps sometimes there's a need to
perform special operations on heap, poweroff memory bank when releasing
memory etc. Therefore some additional data may be required.
Metadata is a point to keep such data.
Signed-off-by: Marcin Szkudlinski <marcin.szkudlinski@intel.com>
Hardware has asynchronous actions where the expectation is to spin on
registers and expressions against those registers for completion of the
action. This provides a common macro to spin, with a delay and timeout,
on such expressions.
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
The temperature sensor used in the clock_control driver requires
multithreading, but this is not compatible with mcuboot builds with
multithreading disabled.
Fixes#41597.
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
According to the board porting guidelines, boards should enable
essential peripherals, such as GPIO/UART/CLOCK_CONTROL/PINCTRL, etc.
Things like PWM/ADC, etc. are not in the "essential" category.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Add the IN_RANGE macro which returns true if a value is
within a supplied range of values (inclusive).
Signed-off-by: Emil Gydesen <emil.gydesen@nordicsemi.no>
bmi160.c module defines DT_DRV_COMPAT, but bmi160_trigger.c doesn't.
This causes a catastrophic chain of events.
The bmi160.c module includes bmi160.h,
in which the macro DT_ANY_INST_ON_BUS_STATUS_OKAY
affects the size of bmi160_bus union.
So bmi160.c defines a bmi160_cfg struct which contains that union.
Now, in bmi160_trigger_init we get a pointer to that config struct.
The fact that this module now includes bmi160.h without
DT_DRV_COMPAT, causes it to think the union is empty.
That doesn't cause compilation error, just undefined behaviour,
In which you address an empty struct fields.
In general, I suggest that someone makes sure it doesn't happen
in other drivers as well. The problem presented here is general,
meaning that if an h file assumes someone defined DT_DRV_COMPAT
before and it doesn't,
it may lead to some weird behaviour, like the one described.
Signed-off-by: Avi Green <avigreen1978@yandex.com>
The SPI cannot be shared between the cores. The MPSL running on
the network core does not support SPI comminucation yet, so the
application core sets FEM's CS to inactive state.
Signed-off-by: Marek Pieta <Marek.Pieta@nordicsemi.no>
Return error code from tx_end callback to bt_mesh_test_send caller. This
will help to understand where test failed.
Signed-off-by: Pavel Vasilyev <pavel.vasilyev@nordicsemi.no>
gpio_pin_interrupt_configure asserts that one of GPIO_INT_ENABLE or
_DISABLE is specified by the caller, and also that GPIO_INT_EDGE is
requested if both states (GPIO_INT_TRIG_BOTH) should interrupt. This
change corrects the misuses in it8xxx2 drivers that cause assertion
failures.
When assertions are disabled the existing code works correctly because
the it8xxx2 GPIO driver assumes that a pin interrupt should be enabled
if _DISABLE is not requested, and the driver only supports edge
triggers but assumes the absence of GPIO_INT_MODE_LEVEL indicates
an edge trigger was requested.
Signed-off-by: Peter Marheine <pmarheine@chromium.org>
Change-Id: I1aaee190ec4cf063f36e25c0c293a91d280e71bb
Add CONFIG_SMP to fvp_baser_aemv8r_smp board.
Fix compile warnings by adding missing header file in arm_mpu.c.
Signed-off-by: Jaxson Han <jaxson.han@arm.com>
This commit mainly fixes the broadcast_ipi issue when one core broadcast
ipi to other cores using gic_raise_sgi. The issue doesn't affect the
functionality of Zephyr SMP but will happen when Zephyr runs on Xen.
Suppose Xen provides 4 CPUs to the Zephyr guest, for example, when cpu0
broadcasts ipi to the rest of the cores, the mask should be 0xE(0b1110),
but for now, Zephyr will send 0xFFFE. So for Xen, it will receive a
target list containing many invalid CPUs which don't exist. My solution
is: to generate the target list according to the online CPUs.
Signed-off-by: Jaxson Han <jaxson.han@arm.com>
Changes ERR to WARN message when relay buffers
run out, as this is not really an error but a
consequence of high traffic.
Signed-off-by: Omkar Kulkarni <omkar.kulkarni@nordicsemi.no>
On 32bit compiler the BIT_MASK(32) generate a warning,
after discussion on #42226 and #42163, advise was to use
BIT64_MASK instead.
Signed-off-by: Julien Massot <julien.massot@iot.bzh>
This board reuse the work did to simulate an
ARMv8-R AArch64 profile core using the FVP platform,
but use the AArch32 profile.
Signed-off-by: Julien Massot <julien.massot@iot.bzh>
This is mostly the same than the aarch64 one, excepted that we
force the armv8r fvp to run in aarch32 profile. So that we can simulate
the Cortex-R52.
Signed-off-by: Julien Massot <julien.massot@iot.bzh>
This is required by drivers which query the current cpu,
at this moment there is no arm aarch32 that use smp,
so it seems safe to consider that the current cpu is
always the first one.
This patch enable the use of the GICv3 driver on
ARM 32bits cpu.
Signed-off-by: Julien Massot <julien.massot@iot.bzh>
These definitions are required to be able to use GICv3
interrupts controller on an ARMv8 AArch32 processor.
Signed-off-by: Julien Massot <julien.massot@iot.bzh>
This is mostly a copy of the existing arm64 implementation,
at the difference that the AArch32 registers do not mention the
execution level.
Signed-off-by: Julien Massot <julien.massot@iot.bzh>
lib_helpers makes easier to access cp15 based registers,
it is inspired from arm64 lib_helpers but use
MRC instead of MRS and use cp15 register.
Definitions on how to access system registers for AArch32
Armv8 processors can be found in the document:
Arm Architecture Reference Manual Armv8,
for Armv8-A architecture profile
Signed-off-by: Julien Massot <julien.massot@iot.bzh>
The ARMv8-R processors always boot into Hyp mode (EL2)
To enter EL1:
Program the HACTLR register because it defaults
to only allowing EL2 accesses. HACTLR controls
whether EL1 can access memory region registers and CPUACTLR.
Program the SPSR before entering EL1.
Other registers default to allowing accesses at EL1 from reset.
Set VBAR to the correct location for the vector table.
Set ELR to point to the entry point of the EL1 code and call ERET.
Signed-off-by: Julien Massot <julien.massot@iot.bzh>
Whenever a stream is attached to an endpoint, the
stream's operation callbacks will be called for the
unicast server.
Signed-off-by: Emil Gydesen <emil.gydesen@nordicsemi.no>
Use DEVICE_DT_GET instead of device_get_binding on the samples. Also,
use the zephyr,canbus chosen device. Note that check for readiness has
not been added as previous code did not check for NULL either.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
When using DMA to transfer over the spi, the spi_stm32_cs_control
is done after enabling the SPI. The same sequence applies
in the transceive_dma function as in transceive function
Signed-off-by: Francois Ramu <francois.ramu@st.com>
The os_mgmt_echo is supposed to return MGMT type error not
Cbor; there was missing translation.
Signed-off-by: Dominik Ermel <dominik.ermel@nordicsemi.no>
The cbor_value_advance at the end of attribute parsing loop could
overwrite err with 0; this could cause loop to fail to break
on error and make cbor_internal_read_object return success, even
if parsing of input buffer failed.
Signed-off-by: Dominik Ermel <dominik.ermel@nordicsemi.no>
As the receive window is now decreased at the TCP module level, other
direct net_context users are also responsible for acknowledging the
received data with net_context_update_recv_wnd() - otherwise, the
communication will stall.
Signed-off-by: Robert Lubos <robert.lubos@nordicsemi.no>
This macro expands to DT_STRING_TOKEN if property exists, otherwise
falls back to default value.
Helpful when a non-required enum binding doesn't mention a default
value, but a default value makes sense to be set in the code.
Including DT_INST_STRING_TOKEN_OR and test code.
Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com>
I2C clock and I2C gpio could be on same gpio group.
Remove assertion that required them to be on different
group.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
rename IMX_CCM_UART_CLK to IMX_CCM_UART4_CLK and
IMX_CCM_UART2_CLK a53 dtsi.
This was missed in a previsous patch set.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This patch fixes ISO data path setup that shall be done for enabled
directions only and removes usage of Path ID = 0xFF which is RFU value.
As per Core 5.3 Vol 4, Part E, 7.8.109
"If the Host attempts to set an output data path using a connection handle
that is for an Isochronous Broadcaster, for an input data path on a
Synchronized Receiver, or for a data path for the direction on a
unidirectional CIS where BN is set to 0, the Controller shall return the
error code Command Disallowed (0x0C)."
Fixes: #43190
Signed-off-by: Mariusz Skamra <mariusz.skamra@codecoup.pl>
Increase main thread stack size so that the sample can be run on
nrf52832 and nrf52840 DKs.
Signed-off-by: Pavel Vasilyev <pavel.vasilyev@nordicsemi.no>
The capabilities callback did not provide information about
the type of the endpoint being configured, making it
impossible for the application to determine if it is a
sink or source endpoint.
Signed-off-by: Emil Gydesen <emil.gydesen@nordicsemi.no>
The unicast client would set the QoS reversed, as the
client should configure it TX parameters for SINK
and RX parameters for source, where it did it the other
way around.
Signed-off-by: Emil Gydesen <emil.gydesen@nordicsemi.no>
Remove functions and and macro uses that otherwise
determined the direction of an audio stream, and instead
use the direction (dir) field of the endpoint instead.
Signed-off-by: Emil Gydesen <emil.gydesen@nordicsemi.no>
Audio streams as defined by the BAP spec does not
support bidirectional audio streams. This commit
updates the API and implementation to match that.
The use a bidirectional CIS with 2 audio stream will
be added in a future commit.
This removes the _IN_ and _OUT_ and _INOUT_ QOS
values, as well as the direction of the codec QOS
struct.
To keep direction for internal use, the direction
has been added to the endpoint struct.
Signed-off-by: Emil Gydesen <emil.gydesen@nordicsemi.no>
Add the BASS client implementation
This is a standalone implementation that
needs to be (heavily) modified for the
broadcast assistant role in the future.
Signed-off-by: Emil Gydesen <emil.gydesen@nordicsemi.no>
Marcin Szkudlinski