This CL is to minimize `CONFIG_SOC_SERIES_XXXX` definitions when we
introduce a new chip series. Most of them are relevant to register
layouts in different npcx soc series. It moves soc-specific register
definitions from `reg_def.h` to its own soc.h file.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Replace Nuvoton NPCX series definitions with new Kconfig definitions in
the npcx drivers. The benefit of this approach is that we won't touch
the npcx driver sources again during introducing a new npcx series next
time.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Move workaround methods for npcx series to soc init functions. If
there's no workaround for this series, drop its soc.c file directly.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
This CL introduces new Flash Interface Unit (FIU) hardware in npcx4
series. The different operations of npcx9 and npcx4 FIU include:
1. 4-byte mode support for DRA mode move to SPI_DEV reg
2. To access the second flash in DRA mode, we need to configure
SPI_DEV_SEL field in BURST_CFG additionally.
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
This CL attempts to implement npcx's flash driver instead of the
original one (npcx spi driver plus spi_nor flash driver).
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Mulin Chao