soc: npcx: replace Nuvoton NPCX series definitions in the npcx drivers

Replace Nuvoton NPCX series definitions with new Kconfig definitions in
the npcx drivers. The benefit of this approach is that we won't touch
the npcx driver sources again during introducing a new npcx series next
time.

Signed-off-by: Mulin Chao <mlchao@nuvoton.com>

drivers/adc/Kconfig.npcx

@@ -11,3 +11,19 @@ config ADC_NPCX
 	  This option enables the ADC driver for NPCX family of
 	  processors.
 	  Say y if you wish to use ADC channels on NPCX MCU.
+
+if ADC_NPCX
+
+config ADC_NPCX_CMP_V1
+	bool "ADC comparator version 1 support"
+	default y if SOC_SERIES_NPCX7 || SOC_SERIES_NPCX9
+	help
+	  This option enables ADC comparator V1 support.
+
+config ADC_NPCX_CMP_V2
+	bool "ADC comparator version 2 support"
+	default y if SOC_SERIES_NPCX4
+	help
+	  This option enables ADC comparator V2 support.
+
+endif #ADC_NPCX

drivers/adc/adc_npcx.c

@@ -168,16 +168,16 @@ static inline void adc_npcx_enable_threshold_detect(const struct device *dev, ui
 	const struct adc_npcx_config *config = dev->config;
 
 	if (enable) {
-#ifdef CONFIG_SOC_SERIES_NPCX4
+#ifdef CONFIG_ADC_NPCX_CMP_V2
 		THEN(config->base) |= BIT(th_sel);
-#else
+#else /* CONFIG_ADC_NPCX_CMP_V1 */
 		THRCTL(config->base, th_sel) |= BIT(NPCX_THRCTL_THEN);
 #endif
 
 	} else {
-#ifdef CONFIG_SOC_SERIES_NPCX4
+#ifdef CONFIG_ADC_NPCX_CMP_V2
 		THEN(config->base) &= ~BIT(th_sel);
-#else
+#else /* CONFIG_ADC_NPCX_CMP_V1 */
 		THRCTL(config->base, th_sel) &= ~BIT(NPCX_THRCTL_THEN);
 #endif
 	}

drivers/espi/Kconfig.npcx

@@ -80,4 +80,10 @@ config ESPI_PERIPHERAL_ACPI_SHM_REGION
 config ESPI_PERIPHERAL_CUSTOM_OPCODE
 	default y
 
+config ESPI_NPCX_SUPP_VW_GPIO
+	bool "Indicates that the eSPI hardware supports virtual wire GPIOs"
+	default y if SOC_SERIES_NPCX9 || SOC_SERIES_NPCX4
+	help
+	  Selected if NPCX series supports virtual wire GPIOs in eSPI module.
+
 endif #ESPI_NPCX

drivers/espi/espi_npcx.c

@@ -164,7 +164,7 @@ static const struct npcx_vw_out_config vw_out_tbl[] = {
 /*  Virtual wire GPIOs for platform level usage (High at Reset state) */
 static const struct npcx_vw_out_config vw_out_gpio_tbl1[] = {
 /* Only NPCX9 and later series support this feature */
-#if !defined(CONFIG_SOC_SERIES_NPCX7)
+#if defined(CONFIG_ESPI_NPCX_SUPP_VW_GPIO)
 	/* index 50h (Out) */
 	NPCX_DT_VW_OUT_CONF(ESPI_VWIRE_SIGNAL_SLV_GPIO_0, vw_slv_gpio_0),
 	NPCX_DT_VW_OUT_CONF(ESPI_VWIRE_SIGNAL_SLV_GPIO_1, vw_slv_gpio_1),

drivers/flash/Kconfig.npcx_fiu

@@ -24,6 +24,8 @@ config FLASH_NPCX_FIU_NOR
 	  This option enables the QSPI NOR Flash driver for NPCX family of
 	  processors.
 
+if FLASH_NPCX_FIU_QSPI
+
 config FLASH_NPCX_FIU_NOR_INIT
 	bool "QSPI NOR flash feature during driver initialization"
 	default y
@@ -32,3 +34,33 @@ config FLASH_NPCX_FIU_NOR_INIT
 	  This option enables the QSPI NOR Flash features such as Quad-Enable,
 	  4-byte address support and so on during driver initialization. Disable
 	  it if QSPI NOR devices are not ready during driver initialization.
+
+config FLASH_NPCX_FIU_DRA_V1
+	bool "Direct Read Access version 1 support"
+	default y if SOC_SERIES_NPCX9
+	help
+	  This option enables DRA V1 support.
+
+config FLASH_NPCX_FIU_DRA_V2
+	bool "Direct Read Access version 2 support"
+	default y if SOC_SERIES_NPCX4
+	help
+	  This option enables DRA V1 support.
+
+config FLASH_NPCX_FIU_SUPP_DRA_4B_ADDR
+	bool "4 byte address support in Direct Read Access mode"
+	default y if FLASH_NPCX_FIU_DRA_V1 || \
+		     FLASH_NPCX_FIU_DRA_V2
+	help
+	  Selected if NPCX series supports 4 byte address mode in Direct Read
+	  Access mode.
+
+config FLASH_NPCX_FIU_SUPP_DRA_2_DEV
+	bool "4 byte address support in Direct Read Access mode"
+	default y if FLASH_NPCX_FIU_DRA_V1 || \
+		     FLASH_NPCX_FIU_DRA_V2
+	help
+	  Selected if NPCX series supports two external SPI devices in Direct
+	  Read Access (DRA) on QSPI bus.
+
+endif #FLASH_NPCX_FIU_QSPI

drivers/flash/flash_npcx_fiu_qspi.c

@@ -99,10 +99,10 @@ static inline void qspi_npcx_config_uma_mode(const struct device *dev,
 static inline void qspi_npcx_config_dra_4byte_mode(const struct device *dev,
 						   const struct npcx_qspi_cfg *qspi_cfg)
 {
-#if !defined(CONFIG_SOC_SERIES_NPCX7) /* NPCX7 doesn't support this feature */
+#if defined(CONFIG_FLASH_NPCX_FIU_SUPP_DRA_4B_ADDR)
 	struct fiu_reg *const inst = HAL_INSTANCE(dev);
 
-#if defined(CONFIG_SOC_SERIES_NPCX9)
+#if defined(CONFIG_FLASH_NPCX_FIU_DRA_V1)
 	if (qspi_cfg->enter_4ba != 0) {
 		if ((qspi_cfg->flags & NPCX_QSPI_SEC_FLASH_SL) != 0) {
 			inst->SPI1_DEV |= BIT(NPCX_SPI1_DEV_FOUR_BADDR_CS11);
@@ -113,12 +113,12 @@ static inline void qspi_npcx_config_dra_4byte_mode(const struct device *dev,
 		inst->SPI1_DEV &= ~(BIT(NPCX_SPI1_DEV_FOUR_BADDR_CS11) |
 				    BIT(NPCX_SPI1_DEV_FOUR_BADDR_CS10));
 	}
-#elif defined(CONFIG_SOC_SERIES_NPCX4)
+#elif defined(CONFIG_FLASH_NPCX_FIU_DRA_V2)
 	if (qspi_cfg->enter_4ba != 0) {
 		SET_FIELD(inst->SPI_DEV, NPCX_SPI_DEV_NADDRB, NPCX_DEV_NUM_ADDR_4BYTE);
 	}
 #endif
-#endif /* CONFIG_SOC_SERIES_NPCX7 */
+#endif /* CONFIG_FLASH_NPCX_FIU_SUPP_DRA_4B_ADDR */
 }
 
 static inline void qspi_npcx_config_dra_mode(const struct device *dev,
@@ -127,7 +127,7 @@ static inline void qspi_npcx_config_dra_mode(const struct device *dev,
 	struct fiu_reg *const inst = HAL_INSTANCE(dev);
 
 	/* Select SPI device number for DRA mode in npcx4 series */
-	if (IS_ENABLED(CONFIG_SOC_SERIES_NPCX4)) {
+	if (IS_ENABLED(CONFIG_FLASH_NPCX_FIU_DRA_V2)) {
 		int spi_dev_num = (qspi_cfg->flags & NPCX_QSPI_SEC_FLASH_SL) != 0 ? 1 : 0;
 
 		SET_FIELD(inst->BURST_CFG, NPCX_BURST_CFG_SPI_DEV_SEL, spi_dev_num);
@@ -270,7 +270,7 @@ static int qspi_npcx_fiu_init(const struct device *dev)
 
 	/* Enable direct access for 2 external SPI devices */
 	if (config->en_direct_access_2dev) {
-		if (IS_ENABLED(CONFIG_SOC_SERIES_NPCX9) || IS_ENABLED(CONFIG_SOC_SERIES_NPCX4)) {
+		if (IS_ENABLED(CONFIG_FLASH_NPCX_FIU_SUPP_DRA_2_DEV)) {
 			inst->FIU_EXT_CFG |= BIT(NPCX_FIU_EXT_CFG_SPI1_2DEV);
 		}
 	}