Changed the default behavior for when we run sanitycheck to match the -R
flag that turns on assertions. Introduced a --disable-asserts option if
we desire to explicitly turn of asserts.
This matches behavior that our CI builds have been doing and addresses
part of #5726.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
We allow the application to have its own dts.fixup. The main use for
this right now is for the build all test to define dummy values for
defines we expect to be generated.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Adds pinmux defines to use I2C2 at PB10/PB11 for
stm32f0-based boards.
Needed for stm32f072b_disco board to use extension
connector
Signed-off-by: Daniel Wagenknecht <wagenknecht@clage.de>
Fixes a bug where in Connection Parameter Request was
initiated by slave role while Encryption Setup had been
started by the peer master.
Fixes: #5823
Signed-off-by: Vinayak Kariappa Chettimada <vich@nordicsemi.no>
This patch reworked logging so that the logging levels are more
finely graded and the locations with non-critical error handling
(below usb_ep_set_stall's) are logged with SYS_LOG_WRN.
Also cleanup, add log domain and fix indents.
Signed-off-by: Johann Fischer <j.fischer@phytec.de>
For SoCs that don't support vector table relocation in hardware, may not
support bootloader like mcuboot.
We introduce a way to relocate vector table in software by forwarding
the control of incoming IRQs to a new vector table which address is save
at fixed SRAM address.
User can change the data in that fixed SRAM address in order to relocate
vector table in software way.
Signed-off-by: Ding Tao <miyatsu@qq.com>
Cortex-M0 do not have the Vector Table Base Address Offset Register, so
Cortex-M0 vector table address can not be changed.
But in some Cortex-M0 SoCs like STM32F0 series, they have some mechanism
that can remap the vector table address to the start address of SRAM.
Use this flag to indicates whether current Cortex-M0 SoC support such a
remap or not.
Signed-off-by: Ding Tao <miyatsu@qq.com>
We want to move to use a common FLASH_DEV_NAME across the various flash
drivers. So samples, tests, or other code can be a bit more generic. So
replace CONFIG_SOC_FLASH_NRF5_DEV_NAME with FLASH_DEV_NAME.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Remove SoCs part dependency of CLOCK_STM32_PLL_PREDIV1 config since
it will only be used on parts having an HSE oscillator, ignored
otherwise.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Rename some legacy upstream and downstream interfaces in
radio_* namespace to ll_* namespace for consistency.
Signed-off-by: Vinayak Kariappa Chettimada <vich@nordicsemi.no>
Introduce flash controller nodes for STM32 SoCs that are supported in
the flash driver. This is a precusor to converting the flash driver on
stm32 over to using device tree.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
In order to be able to build MCUboot for nRF51 we require the flash
driver name in the nRF51 soc.h header.
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
Corrected the board name in the configuration short
description string. It was the old Simple_process name which was
replaced with native_posix
Corrected also the comment/title in the "Board Options" menu
Signed-off-by: Alberto Escolar Piedras <alpi@oticon.com>
The native SOC Kconfig file was still referring to the old
configuration option SOC_INF_CLOCK which was replaced with
SOC_POSIX.
This produced a warning on configuration which is now fixed
Signed-off-by: Alberto Escolar Piedras <alpi@oticon.com>
Refactor Kconfig and CMakelists.txt to be able to
conditionally compile in BT_LL_SW variant in the controller
subsystem. This is done to support future controller with
vendor specific variant implementations.
Signed-off-by: Vinayak Kariappa Chettimada <vich@nordicsemi.no>
Add conditional compilation and move code to support
building a non-connectable Bluetooth shell application.
Signed-off-by: Vinayak Kariappa Chettimada <vich@nordicsemi.no>
When we updated the Nordic SoCs for getting flash controller label/name
from dts, we missed updating the 96b_nitrogen/dts.fixup file.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
We duplicate a lot of fixup info per board which could be done at the
SoC family level. So introduce the concept of DTS_SOC_FIXUP_FILE which
we default to arch/<ARCH>/soc/<SOC_FAMILY>/<SOC_SERIES>/dts.fixup.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
The work-around previously setting ARC builds to use -O2 to fix an
ADC bug #3797 is no longer needed, we should this patch and revert
to the default -Os flag to optimize for smaller size.
Signed-off-by: Jimmy Huang <jimmy.huang@intel.com>
To get coverage data from all samples and tests, enable this by default.
Right now we only get coverage data from tests, however many samples we
currently have can run natively and can generate more coverage and
testing.
This should be removed once we have tests provide better coverage.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Those are added by sanitycheck, no need to have them enabled in the
project by default.
CONFIG_DEBUG is causing issues on qemu_nios2, see #5743.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
The demo can be configured to use different object types for its
synchronization, so test all of them.
The demo can also be configured to work with static objects or dynamic
objects, byt default the demo uses dynamic objects, add a test for
static objects.
Also, the demo can be configured to work with threads of the same
priority or not, so enable both options for testing
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Do not build for some unsupported architecture and exclude ARM qemu
platform due to bug #5735.
STACK_ALIGN 0x8
MPU STACK GUARD Test
Canary Initial Value = 0xf0cacc1a threads 0x200010e0
Canary = 0x20000240 Test not passed.
***** BUS FAULT *****
Executing thread ID (thread): 0x200010e0
Faulting instruction address: 0x209c
Imprecise data bus error
Fatal fault in thread 0x200010e0! Aborting.
***** HARD FAULT *****
Fault escalation (see below)
***** BUS FAULT *****
Executing thread ID (thread): 0x200010e0
Faulting instruction address: 0x1f4
Imprecise data bus error
Fatal fault in ISR! Spinning...
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Evaluate output from sample and record success/failure.
Enable on other platforms, this should not be whitelisted.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
We can now send a signal and exit gracefully. This is to maintain
consistency across other runners and samples that can run natively but
do not have a test hook or macro to kill the application in completion.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
The output of those samples can be parsed and verified by sanitycheck,
so lets use the console harness for this.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Kumar Gala