This commit adds an enum to the `arch` field of the Twister platform
schema. This helps better filter boards for testcases which use
architecture-based filters, and helps maintain uniformity in naming
convetion.
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
Fix conflict between commit ce24394437 ("llext: add object test case")
and commit 1408d1e5b8 ("tests: llext: compile architectures not
supported yet") which were tested separately but merged at the same
time.
Github "Merge Queues" can avoid this (and save resources) but:
- they're not used by Zephyr CI
- they provide confusing feedback
Signed-off-by: Marc Herbert <marc.herbert@intel.com>
Remove SCO security management code block.
Currently, security related checks are not
necessary. It can be added if needed.
Signed-off-by: Lyle Zhu <lyle.zhu@nxp.com>
Call bt_sco_server_register to register SCO
server. Manage the SCO connection request.
Get SCO connect/disconnect status via SCO
channel ops.
Notify the uppper layer of the SCO connection
status changes through bt_hfp_hf_cb::
sco_connected and bt_hfp_hf_cb::
sco_disconnected.
Signed-off-by: Lyle Zhu <lyle.zhu@nxp.com>
Currently, SCO connections and disconnections
are agnostic to upper-layer.
Add two functions, bt_sco_connected and
bt_sco_disconnected, to notify the SCO
connect changes.
For Central side, pass "struct bt_sco_chan"
object when calling bt_conn_create_sco. it
uses to manage the SCO channel for upper-
layer.
For Peripheral side, two functions
bt_sco_server_register and
bt_sco_server_unregister are added to monitor
SCO connection request for upper-layer. The
upper-layer could accept or reject SCO connect
When the connection request received. If the
connect is accepted, the "struct bt_sco_chan"
object could be passed by "sco_server->accept".
Signed-off-by: Lyle Zhu <lyle.zhu@nxp.com>
Add support for propagating SOC_NRF54LX_DISABLE_FICR_TRIMCNF and
SOC_NRF54LX_SKIP_GLITCHDETECTOR_DISABLE values to nrfx.
Signed-off-by: Magdalena Pastula <magdalena.pastula@nordicsemi.no>
Enable testing of all CiA recommended bitrates on the following
simulated/emulated boards:
- native_sim
- native_sim_64
- native_posix
- native_posix_64
- qemu_x86
- qemu_x86_64
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Use the CAN clock and configuration ranges recommended by CAN in Automation
(CiA). Adjust the CAN shell test, which makes use of the fake CAN
controller driver, to match the new timing limits.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Some CAN controllers may be unable to meet all bitrates due to timing
restrictions, but assert that at least one of the tested bitrates was
supported.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Add tests for all CAN bitrates recommended by CAN in Automation (CiA). The
newly added bitrate tests are guarded by new, local Kconfig option
(CONFIG_TEST_ALL_BITRATES) to avoid breaking existing board tests.
Some boards may need adjustments to their CAN core clock in order to pass
the newly added tests. Once a board is confirmed to meet these additional
checks, this Kconfig can be enabled for that board to avoid future
regressions.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Remove tests for additional sample points as this does not provide any real
value.
The purpose of this test suite is to see if the selected CAN clock allows
meeting the standard bitrates and sample points used by Zephyr. Any
tweaking needed for a specific board or system design is left up to the
user and not something that can be covered by testing a few additional
sample point locations.
Change a few comments and remove an unneeded conditional while here.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Move the tests for using invalid sample points from the CAN timing tests to
the CAN API tests as these are validating basic API behavior.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Move the tests for setting a too high bitrate from the CAN timing tests to
the CAN API tests as these are validating basic API behavior.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Move the test for setting the minimum/maximum supported timing parameters
from the CAN timing tests to the CAN API tests as these are validating
basic API behavior.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
The codecs used for the bap bt_bap_stream_config was only
valid for the lifetime of the procedure, which meant
that by the end of the procedure the stream->codec_cfg
became invalid.
This is fixed by using the pointer provided to the
CAP API, and documentating the lifetime of the codec_cfg.
Signed-off-by: Emil Gydesen <emil.gydesen@nordicsemi.no>
IGMP queries sent out by a proxy querier can have
a source IP address 0.0.0.0
Allow these incoming packets.
Fixes#69917
Signed-off-by: Savin Weeraratne <savin.weeraratne@audinate.com>
When we receive Router Advertisement with life time,
we will add this as default router, like typing command "net iface"
and has show below
IPv6 default router :
fe80:xxxx::xxxx
When this default router is backend A and
we ping backend B with link local address,
we will use default router A and send echo request
to backend A instead of B, which will receive Redirect and no reply.
Fix it by link local address does not check route.
Signed-off-by: Fengming Ye <frank.ye@nxp.com>
For now llext supports a very limited number of architectures. This
restriction is enforced by add_llext_target() in CMake at configuration
time.
Add a new `LOADER_BUILD_ONLY` conditional in tests/subsys/llext/simple/
and a new `llext.simple.loader_build`, `build_only` test that does not
invoke `add_llext_target()` and only compiles the llext framework code.
This helps find and fix bugs in `subsys/llext/*.c` and make it ready to
be used when add_llext_target() limitations are lifted.
Note this is pure `tests/` change without any change in the actual llext
framework code. The existing test is only modified to conditionally
invoke add_llext_target().
Signed-off-by: Marc Herbert <marc.herbert@intel.com>
native_posix is being replaced with native_sim, let's
have these tests be run on native_sim instead.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
GATT/SR/GAS/BV-01-C has just broken due to what appears
like a minor timing change.
This indicates the test may be too time sensitive.
Just reordering the tests, it passes again.
So let's reorder the test list, and we get the minor
benefit of havign them move alphabetically ordered.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
Remove incorrect return statements in the `z_impl_mdio_bus_enable` and
`z_impl_mdio_bus_disable` functions within the MDIO driver API.
These functions are intended to call the `bus_enable` and `bus_disable`
methods of the MDIO driver API without returning a value,
as they are defined to return void.
Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
This replacement for the `nordic-ppr-ram` snippet does the opposite:
enable PPR execution in place from MRAM.
Signed-off-by: Grzegorz Swiderski <grzegorz.swiderski@nordicsemi.no>
The `nordic-ppr` snippet can now be used instead, since RAM execution is
default for PPR.
Signed-off-by: Grzegorz Swiderski <grzegorz.swiderski@nordicsemi.no>
In practice, PPR is intended to be running code from RAM, so make this
the default choice for the `nrf54h20dk/nrf54h20/cpuppr` board target.
Keep the MRAM execution option as a `xip` variant of that target,
replacing the `ram` one.
Align the default `cpuapp` configuration for copying PPR's image to RAM
before it boots the child processor.
Signed-off-by: Grzegorz Swiderski <grzegorz.swiderski@nordicsemi.no>
nRF54H20 PDK is superseded by nRF54H20 DK and will no longer be
supported.
The board was superseded by nRF54H20 DK.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Add targets for the Application, Radio, and PPR cores in the nRF54H20
SoC on the nRF54H20 DK board.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Add definition of the nRF54H20 SoC with its Application, Radio,
and Peripheral Processor (PPR) cores and an initial set of
peripherals.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
For certain peripheral signal lines in nRF54H20, it is required
to set the clockpin bitfield for pins assigned to them, otherwise
the peripheral may not work properly, for example, there will be
no output from UART.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
- add new entries that appeared in nrfx 3.4.0
- correct the default IRQ priority value for PPR (it is intended to be
the lowest prority, so unlike for ARM cores, for RISC-V it should be
the lowest value)
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Enable support for dma controller on RD RW612 BGA board, and add overlay
to enable board in dma loop transfer test
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
RW61x DMA has the *unique* restriction that DMA access is not routed
through the FlexSPI cache engine, only via the non-cached address space.
To enable DMA to read from the FlexSPI AHB space directly, fixup any
address passed to the DMA engine that is in the FlexSPI AHB cached
region to be in the non cached region
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Filip Kokosinski