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arch: riscv: add macro to access hardware registers 

Add macros to read / write hardware registers.

Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Signed-off-by: Yong Cong Sin <yongcong.sin@gmail.com>
This commit is contained in:
Yong Cong Sin 2024-11-10 13:51:02 +08:00 committed by Dan Kalowsky
parent d267402404
commit de3a845612
1 changed files with 19 additions and 0 deletions
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19
include/zephyr/arch/riscv/reg.h Normal file
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/*
* Copyright (c) 2024 Meta Platforms
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_ZEPHYR_ARCH_RISCV_REG_H_
#define ZEPHYR_INCLUDE_ZEPHYR_ARCH_RISCV_REG_H_
#define reg_read(reg) \
({ \
register unsigned long __rv; \
__asm__ volatile("mv %0, " STRINGIFY(reg) : "=r"(__rv)); \
__rv; \
})
#define reg_write(reg, val) ({ __asm__("mv " STRINGIFY(reg) ", %0" : : "r"(val)); })
#endif /* ZEPHYR_INCLUDE_ZEPHYR_ARCH_RISCV_REG_H_ */