From de3a845612b6d4f5be53e79525c4b3d82521824c Mon Sep 17 00:00:00 2001 From: Yong Cong Sin Date: Sun, 10 Nov 2024 13:51:02 +0800 Subject: [PATCH] arch: riscv: add macro to access hardware registers Add macros to read / write hardware registers. Signed-off-by: Yong Cong Sin Signed-off-by: Yong Cong Sin --- include/zephyr/arch/riscv/reg.h | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) create mode 100644 include/zephyr/arch/riscv/reg.h diff --git a/include/zephyr/arch/riscv/reg.h b/include/zephyr/arch/riscv/reg.h new file mode 100644 index 00000000000..6d3b2d88b17 --- /dev/null +++ b/include/zephyr/arch/riscv/reg.h @@ -0,0 +1,19 @@ +/* + * Copyright (c) 2024 Meta Platforms + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_ZEPHYR_ARCH_RISCV_REG_H_ +#define ZEPHYR_INCLUDE_ZEPHYR_ARCH_RISCV_REG_H_ + +#define reg_read(reg) \ + ({ \ + register unsigned long __rv; \ + __asm__ volatile("mv %0, " STRINGIFY(reg) : "=r"(__rv)); \ + __rv; \ + }) + +#define reg_write(reg, val) ({ __asm__("mv " STRINGIFY(reg) ", %0" : : "r"(val)); }) + +#endif /* ZEPHYR_INCLUDE_ZEPHYR_ARCH_RISCV_REG_H_ */