drivers: clock_control: add npcm clock control driver
Add npcm clock control driver. Signed-off-by: James Chiang <cpchiang1@nuvoton.com> Signed-off-by: Joseph Liu <kwliu@nuvoton.com> Signed-off-by: Alan Yang <tyang1@nuvoton.com>
This commit is contained in:
James Chiang
Anas Nashif
parent
9542166589
commit
bfa1e36789
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@ -19,6 +19,7 @@ zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_MCUX_SCG clock_cont
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zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_MCUX_SCG_K4 clock_control_mcux_scg_k4.c)
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zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_MCUX_SIM clock_control_mcux_sim.c)
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zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_MCUX_SYSCON clock_control_mcux_syscon.c)
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zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_NPCM clock_control_npcm.c)
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zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_NPCX clock_control_npcx.c)
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zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_NRF clock_control_nrf.c)
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zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_NRF_DRIVER_CALIBRATION nrf_clock_calibration.c)
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@ -50,6 +50,8 @@ source "drivers/clock_control/Kconfig.mcux_sim"
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source "drivers/clock_control/Kconfig.mcux_syscon"
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source "drivers/clock_control/Kconfig.npcm"
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source "drivers/clock_control/Kconfig.npcx"
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source "drivers/clock_control/Kconfig.rv32m1"
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@ -0,0 +1,11 @@
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# NPCM Clock controller driver configuration options
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# Copyright (c) 2024 Nuvoton Technology Corporation.
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# SPDX-License-Identifier: Apache-2.0
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config CLOCK_CONTROL_NPCM
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bool "NPCM clock controller driver"
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default y
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depends on DT_HAS_NUVOTON_NPCM_PCC_ENABLED
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help
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Enable support for NPCM clock controller driver.
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@ -0,0 +1,365 @@
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/*
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* Copyright (c) 2024 Nuvoton Technology Corporation.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT nuvoton_npcm_pcc
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#include <soc.h>
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#include <zephyr/drivers/clock_control.h>
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#include <zephyr/dt-bindings/clock/npcm_clock.h>
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#include <zephyr/logging/log.h>
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LOG_MODULE_REGISTER(clock_control_npcm, LOG_LEVEL_ERR);
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/* Driver config */
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struct npcm_pcc_config {
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/* cdcg device base address */
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uintptr_t base_cdcg;
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/* pmc device base address */
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uintptr_t base_pmc;
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};
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/*
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* Core Domain Clock Generator (CDCG) device registers
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*/
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struct cdcg_reg {
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/* High Frequency Clock Generator (HFCG) registers */
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/* 0x000: HFCG Control */
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volatile uint8_t hfcgctrl;
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volatile uint8_t reserved1;
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/* 0x002: HFCG M Low Byte Value */
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volatile uint8_t hfcgml;
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volatile uint8_t reserved2;
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/* 0x004: HFCG M High Byte Value */
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volatile uint8_t hfcgmh;
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volatile uint8_t reserved3;
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/* 0x006: HFCG N Value */
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volatile uint8_t hfcgn;
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volatile uint8_t reserved4;
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/* 0x008: HFCG Prescaler */
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volatile uint8_t hfcgp;
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volatile uint8_t reserved5[7];
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/* 0x010: HFCG Bus Clock Dividers */
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volatile uint8_t hfcbcd;
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volatile uint8_t reserved6;
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/* 0x012: HFCG Bus Clock Dividers */
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volatile uint8_t hfcbcd1;
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volatile uint8_t reserved7;
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/* 0x014: HFCG Bus Clock Dividers */
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volatile uint8_t hfcbcd2;
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volatile uint8_t reserved12[8];
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/* 0x01d: HFCG Bus Clock Dividers */
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volatile uint8_t hfcbcd3;
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};
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/* clock bus references */
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#define NPCM_CLOCK_BUS_LFCLK 0
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#define NPCM_CLOCK_BUS_OSC 1
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#define NPCM_CLOCK_BUS_FIU 2
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#define NPCM_CLOCK_BUS_I3C 3
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#define NPCM_CLOCK_BUS_CORE 4
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#define NPCM_CLOCK_BUS_APB1 5
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#define NPCM_CLOCK_BUS_APB2 6
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#define NPCM_CLOCK_BUS_APB3 7
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#define NPCM_CLOCK_BUS_APB4 8
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#define NPCM_CLOCK_BUS_AHB6 9
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#define NPCM_CLOCK_BUS_FMCLK 10
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#define NPCM_CLOCK_BUS_USB20_CLK 11
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#define NPCM_CLOCK_BUS_SIO_CLK 12
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/* clock enable/disable references */
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#define NPCM_PWDWN_CTL0 0
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#define NPCM_PWDWN_CTL1 1
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#define NPCM_PWDWN_CTL2 2
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#define NPCM_PWDWN_CTL3 3
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#define NPCM_PWDWN_CTL4 4
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#define NPCM_PWDWN_CTL5 5
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#define NPCM_PWDWN_CTL6 6
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#define NPCM_PWDWN_CTL7 7
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/* CDCG register fields */
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#define NPCM_HFCGCTRL_LOAD 0
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#define NPCM_HFCGCTRL_LOCK 2
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#define NPCM_HFCGCTRL_CLK_CHNG 7
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/* Clock settings from pcc node */
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/* Target OFMCLK freq */
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#define OFMCLK DT_PROP(DT_NODELABEL(pcc), clock_frequency)
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/* Core clock prescaler */
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#define FPRED_VAL (DT_PROP(DT_NODELABEL(pcc), core_prescaler) - 1)
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/* APB1 clock divider */
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#define APB1DIV_VAL (DT_PROP(DT_NODELABEL(pcc), apb1_prescaler) - 1)
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/* APB2 clock divider */
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#define APB2DIV_VAL (DT_PROP(DT_NODELABEL(pcc), apb2_prescaler) - 1)
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/* APB3 clock divider */
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#define APB3DIV_VAL (DT_PROP(DT_NODELABEL(pcc), apb3_prescaler) - 1)
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/* AHB6 clock divider*/
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#define AHB6DIV_VAL (DT_PROP(DT_NODELABEL(pcc), ahb6_prescaler) - 1)
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/* FIU clock divider */
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#define FIUDIV_VAL (DT_PROP(DT_NODELABEL(pcc), fiu_prescaler) - 1)
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/* I3C clock divider */
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#define I3CDIV_VAL (DT_PROP(DT_NODELABEL(pcc), i3c_prescaler) - 1)
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/* Core domain clock */
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#define CORE_CLK (OFMCLK / DT_PROP(DT_NODELABEL(pcc), core_prescaler))
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/* Low Frequency clock */
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#define LFCLK 32768
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/* FMUL clock */
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#define FMCLK OFMCLK /* FMUL clock = OFMCLK */
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/* APBs source clock */
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#define APBSRC_CLK OFMCLK
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/* USB2.0 clock */
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#define USB20_CLK 12000000
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/* SIO clock */
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#define SIO_CLK 48000000
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/* Get APB clock freq */
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#define NPCM_APB_CLOCK(no) (APBSRC_CLK / (APB##no##DIV_VAL + 1))
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struct freq_multiplier_t {
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uint32_t ofmclk;
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uint8_t hfcgn;
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uint8_t hfcgmh;
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uint8_t hfcgml;
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};
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static struct freq_multiplier_t freq_multiplier[] = {
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{.ofmclk = 100000000, .hfcgn = 0x82, .hfcgmh = 0x0B, .hfcgml = 0xEC},
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{.ofmclk = 96000000, .hfcgn = 0x82, .hfcgmh = 0x0B, .hfcgml = 0x72},
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{.ofmclk = 80000000, .hfcgn = 0x82, .hfcgmh = 0x09, .hfcgml = 0x89},
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{.ofmclk = 66000000, .hfcgn = 0x82, .hfcgmh = 0x07, .hfcgml = 0xDE},
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{.ofmclk = 50000000, .hfcgn = 0x02, .hfcgmh = 0x0B, .hfcgml = 0xEC},
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{.ofmclk = 48000000, .hfcgn = 0x02, .hfcgmh = 0x0B, .hfcgml = 0x72},
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{.ofmclk = 40000000, .hfcgn = 0x02, .hfcgmh = 0x09, .hfcgml = 0x89},
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{.ofmclk = 33000000, .hfcgn = 0x02, .hfcgmh = 0x07, .hfcgml = 0xDE}};
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struct clk_cfg_t {
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uint32_t clock_id;
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uint16_t bus;
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};
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static struct clk_cfg_t clk_cfg[] = {
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{.clock_id = NPCM_CLOCK_PWM_I, .bus = NPCM_CLOCK_BUS_LFCLK},
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{.clock_id = NPCM_CLOCK_PWM_J, .bus = NPCM_CLOCK_BUS_LFCLK},
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{.clock_id = NPCM_CLOCK_I3CI, .bus = NPCM_CLOCK_BUS_APB3},
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{.clock_id = NPCM_CLOCK_UART3, .bus = NPCM_CLOCK_BUS_APB2},
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{.clock_id = NPCM_CLOCK_UART2, .bus = NPCM_CLOCK_BUS_APB2},
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{.clock_id = NPCM_CLOCK_FIU, .bus = NPCM_CLOCK_BUS_FIU},
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{.clock_id = NPCM_CLOCK_USB20, .bus = NPCM_CLOCK_BUS_USB20_CLK},
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{.clock_id = NPCM_CLOCK_UART, .bus = NPCM_CLOCK_BUS_APB2},
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{.clock_id = NPCM_CLOCK_PWM_A, .bus = NPCM_CLOCK_BUS_LFCLK},
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{.clock_id = NPCM_CLOCK_PWM_B, .bus = NPCM_CLOCK_BUS_LFCLK},
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{.clock_id = NPCM_CLOCK_PWM_C, .bus = NPCM_CLOCK_BUS_LFCLK},
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{.clock_id = NPCM_CLOCK_PWM_D, .bus = NPCM_CLOCK_BUS_LFCLK},
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{.clock_id = NPCM_CLOCK_PWM_E, .bus = NPCM_CLOCK_BUS_LFCLK},
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{.clock_id = NPCM_CLOCK_PWM_F, .bus = NPCM_CLOCK_BUS_LFCLK},
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{.clock_id = NPCM_CLOCK_PWM_G, .bus = NPCM_CLOCK_BUS_LFCLK},
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{.clock_id = NPCM_CLOCK_PWM_H, .bus = NPCM_CLOCK_BUS_LFCLK},
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{.clock_id = NPCM_CLOCK_SMB1, .bus = NPCM_CLOCK_BUS_APB3},
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{.clock_id = NPCM_CLOCK_SMB2, .bus = NPCM_CLOCK_BUS_APB3},
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{.clock_id = NPCM_CLOCK_SMB3, .bus = NPCM_CLOCK_BUS_APB3},
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{.clock_id = NPCM_CLOCK_SMB4, .bus = NPCM_CLOCK_BUS_APB3},
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{.clock_id = NPCM_CLOCK_SMB5, .bus = NPCM_CLOCK_BUS_APB3},
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{.clock_id = NPCM_CLOCK_SMB6, .bus = NPCM_CLOCK_BUS_APB3},
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{.clock_id = NPCM_CLOCK_ITIM1, .bus = NPCM_CLOCK_BUS_LFCLK},
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{.clock_id = NPCM_CLOCK_ITIM2, .bus = NPCM_CLOCK_BUS_LFCLK},
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{.clock_id = NPCM_CLOCK_ITIM3, .bus = NPCM_CLOCK_BUS_LFCLK},
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{.clock_id = NPCM_CLOCK_ADC, .bus = NPCM_CLOCK_BUS_APB1},
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{.clock_id = NPCM_CLOCK_PECI, .bus = NPCM_CLOCK_BUS_FMCLK},
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{.clock_id = NPCM_CLOCK_UART4, .bus = NPCM_CLOCK_BUS_APB2},
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{.clock_id = NPCM_CLOCK_ESPI, .bus = NPCM_CLOCK_BUS_APB3},
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{.clock_id = NPCM_CLOCK_SMB7, .bus = NPCM_CLOCK_BUS_APB3},
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{.clock_id = NPCM_CLOCK_SMB8, .bus = NPCM_CLOCK_BUS_APB3},
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{.clock_id = NPCM_CLOCK_SMB9, .bus = NPCM_CLOCK_BUS_APB3},
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{.clock_id = NPCM_CLOCK_SMB10, .bus = NPCM_CLOCK_BUS_APB3},
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{.clock_id = NPCM_CLOCK_SMB11, .bus = NPCM_CLOCK_BUS_APB3},
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{.clock_id = NPCM_CLOCK_SMB12, .bus = NPCM_CLOCK_BUS_APB3},
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};
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/* PMC multi-registers */
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#define NPCM_PWDWN_CTL_OFFSET(n) (((n) < 7) ? (0x07 + n) : (0x15 + (n - 7)))
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#define NPCM_PWDWN_CTL(base, n) (*(volatile uint8_t *)(base + NPCM_PWDWN_CTL_OFFSET(n)))
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#define NPCM_CLOCK_REG_OFFSET(n) ((n) >> 3)
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#define NPCM_CLOCK_REG_BIT_OFFSET(n) ((n) & 0x7)
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#define DRV_CONFIG(dev) ((const struct npcm_pcc_config *)(dev)->config)
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/* Clock controller local functions */
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static struct clk_cfg_t *npcm_get_cfg(clock_control_subsys_t sub_system)
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{
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uint32_t clk_id = (uint32_t)sub_system;
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uint32_t i;
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for (i = 0; i < ARRAY_SIZE(clk_cfg); i++) {
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if (clk_cfg[i].clock_id == clk_id) {
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return &clk_cfg[i];
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}
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}
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return NULL;
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}
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static inline int npcm_clock_control_on(const struct device *dev, clock_control_subsys_t sub_system)
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{
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uint32_t clk_id = (uint32_t)sub_system;
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struct clk_cfg_t *priv;
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const uint32_t pmc_base = DRV_CONFIG(dev)->base_pmc;
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priv = npcm_get_cfg(sub_system);
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if (!priv) {
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LOG_ERR("Unsupported clock id %d", clk_id);
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return -EINVAL;
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}
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/* Clear related PD (Power-Down) bit of module to turn on clock */
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NPCM_PWDWN_CTL(pmc_base, NPCM_CLOCK_REG_OFFSET(priv->clock_id)) &=
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~(BIT(NPCM_CLOCK_REG_BIT_OFFSET(priv->clock_id)));
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return 0;
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}
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static inline int npcm_clock_control_off(const struct device *dev,
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clock_control_subsys_t sub_system)
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{
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uint32_t clk_id = (uint32_t)sub_system;
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struct clk_cfg_t *priv;
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const uint32_t pmc_base = DRV_CONFIG(dev)->base_pmc;
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priv = npcm_get_cfg(sub_system);
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if (!priv) {
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LOG_ERR("Unsupported clock id %d", clk_id);
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return -EINVAL;
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}
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/* Set related PD (Power-Down) bit of module to turn off clock */
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NPCM_PWDWN_CTL(pmc_base, NPCM_CLOCK_REG_OFFSET(priv->clock_id)) |=
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~(BIT(NPCM_CLOCK_REG_BIT_OFFSET(priv->clock_id)));
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return 0;
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}
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static int npcm_clock_control_get_subsys_rate(const struct device *dev,
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clock_control_subsys_t sub_system, uint32_t *rate)
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{
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ARG_UNUSED(dev);
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uint32_t clk_id = (uint32_t)sub_system;
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struct clk_cfg_t *priv;
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priv = npcm_get_cfg(sub_system);
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if (!priv) {
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LOG_ERR("Unsupported clock id %d", clk_id);
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return -EINVAL;
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}
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switch (priv->bus) {
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case NPCM_CLOCK_BUS_APB1:
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*rate = NPCM_APB_CLOCK(1);
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break;
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case NPCM_CLOCK_BUS_APB2:
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*rate = NPCM_APB_CLOCK(2);
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break;
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case NPCM_CLOCK_BUS_APB3:
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*rate = NPCM_APB_CLOCK(3);
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break;
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case NPCM_CLOCK_BUS_AHB6:
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*rate = CORE_CLK / (AHB6DIV_VAL + 1);
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break;
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case NPCM_CLOCK_BUS_FIU:
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*rate = CORE_CLK / (FIUDIV_VAL + 1);
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break;
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case NPCM_CLOCK_BUS_I3C:
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*rate = CORE_CLK / (I3CDIV_VAL + 1);
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break;
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case NPCM_CLOCK_BUS_CORE:
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*rate = CORE_CLK;
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break;
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case NPCM_CLOCK_BUS_LFCLK:
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*rate = LFCLK;
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break;
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case NPCM_CLOCK_BUS_FMCLK:
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*rate = FMCLK;
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break;
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case NPCM_CLOCK_BUS_USB20_CLK:
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*rate = USB20_CLK;
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break;
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case NPCM_CLOCK_BUS_SIO_CLK:
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*rate = SIO_CLK;
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break;
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default:
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*rate = 0U;
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/* Invalid parameters */
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return -EINVAL;
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}
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return 0;
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}
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/* Clock controller driver registration */
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static struct clock_control_driver_api npcm_clock_control_api = {
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.on = npcm_clock_control_on,
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.off = npcm_clock_control_off,
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.get_rate = npcm_clock_control_get_subsys_rate,
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};
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static int npcm_clock_control_init(const struct device *dev)
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{
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struct cdcg_reg *const priv = (struct cdcg_reg *)(DRV_CONFIG(dev)->base_cdcg);
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struct freq_multiplier_t *freq_p;
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int i;
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for (i = 0; i < ARRAY_SIZE(freq_multiplier); i++) {
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if (freq_multiplier[i].ofmclk == OFMCLK) {
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freq_p = &freq_multiplier[i];
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break;
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}
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}
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if (i >= ARRAY_SIZE(freq_multiplier)) {
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LOG_ERR("Unsupported OFMCLK frequency %d", OFMCLK);
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return -EINVAL;
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}
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/*
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* Resetting the OFMCLK (even to the same value) will make the clock
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* unstable for a little which can affect peripheral communication like
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* eSPI. Skip this if not needed.
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*/
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if (priv->hfcgn != freq_p->hfcgn || priv->hfcgml != freq_p->hfcgml ||
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priv->hfcgmh != freq_p->hfcgmh) {
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/*
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* Configure frequency multiplier M/N values according to
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* the requested OFMCLK (Unit:Hz).
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*/
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priv->hfcgn = freq_p->hfcgn;
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priv->hfcgml = freq_p->hfcgml;
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priv->hfcgmh = freq_p->hfcgmh;
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/* Load M and N values into the frequency multiplier */
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priv->hfcgctrl |= BIT(NPCM_HFCGCTRL_LOAD);
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/* Wait for stable */
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while (sys_test_bit(priv->hfcgctrl, NPCM_HFCGCTRL_CLK_CHNG))
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;
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}
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/* Set all clock prescalers of core and peripherals. */
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priv->hfcgp = (FPRED_VAL << 4) | AHB6DIV_VAL;
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priv->hfcbcd = APB1DIV_VAL | (APB2DIV_VAL << 4);
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priv->hfcbcd1 = (I3CDIV_VAL << 2) | FIUDIV_VAL;
|
||||
priv->hfcbcd2 = APB3DIV_VAL;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
const struct npcm_pcc_config pcc_config = {
|
||||
.base_cdcg = DT_INST_REG_ADDR_BY_NAME(0, cdcg),
|
||||
.base_pmc = DT_INST_REG_ADDR_BY_NAME(0, pmc),
|
||||
};
|
||||
|
||||
DEVICE_DT_INST_DEFINE(0, &npcm_clock_control_init, NULL, NULL, &pcc_config, PRE_KERNEL_1,
|
||||
CONFIG_KERNEL_INIT_PRIORITY_OBJECTS, &npcm_clock_control_api);
|
||||
|
|
@ -0,0 +1,72 @@
|
|||
/*
|
||||
* Copyright (c) 2024 Nuvoton Technology Corporation.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_NPCM_CLOCK_H_
|
||||
#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_NPCM_CLOCK_H_
|
||||
|
||||
/* clock bus references */
|
||||
#define NPCM_CLOCK_GROUP_OFFSET(N) ((N) << 3)
|
||||
|
||||
#define NPCM_CLOCK_PWM_I (NPCM_CLOCK_GROUP_OFFSET(0) + 0)
|
||||
#define NPCM_CLOCK_PWM_J (NPCM_CLOCK_GROUP_OFFSET(0) + 1)
|
||||
#define NPCM_CLOCK_I3CI (NPCM_CLOCK_GROUP_OFFSET(0) + 2)
|
||||
#define NPCM_CLOCK_UART3 (NPCM_CLOCK_GROUP_OFFSET(0) + 5)
|
||||
#define NPCM_CLOCK_UART2 (NPCM_CLOCK_GROUP_OFFSET(0) + 6)
|
||||
#define NPCM_CLOCK_SPIM (NPCM_CLOCK_GROUP_OFFSET(1) + 0)
|
||||
#define NPCM_CLOCK_FIU (NPCM_CLOCK_GROUP_OFFSET(1) + 2)
|
||||
#define NPCM_CLOCK_USB20 (NPCM_CLOCK_GROUP_OFFSET(1) + 3)
|
||||
#define NPCM_CLOCK_UART (NPCM_CLOCK_GROUP_OFFSET(1) + 4)
|
||||
#define NPCM_CLOCK_MFT1 (NPCM_CLOCK_GROUP_OFFSET(1) + 5)
|
||||
#define NPCM_CLOCK_MFT2 (NPCM_CLOCK_GROUP_OFFSET(1) + 6)
|
||||
#define NPCM_CLOCK_MFT3 (NPCM_CLOCK_GROUP_OFFSET(1) + 7)
|
||||
#define NPCM_CLOCK_PWM_A (NPCM_CLOCK_GROUP_OFFSET(2) + 0)
|
||||
#define NPCM_CLOCK_PWM_B (NPCM_CLOCK_GROUP_OFFSET(2) + 1)
|
||||
#define NPCM_CLOCK_PWM_C (NPCM_CLOCK_GROUP_OFFSET(2) + 2)
|
||||
#define NPCM_CLOCK_PWM_D (NPCM_CLOCK_GROUP_OFFSET(2) + 3)
|
||||
#define NPCM_CLOCK_PWM_E (NPCM_CLOCK_GROUP_OFFSET(2) + 4)
|
||||
#define NPCM_CLOCK_PWM_F (NPCM_CLOCK_GROUP_OFFSET(2) + 5)
|
||||
#define NPCM_CLOCK_PWM_G (NPCM_CLOCK_GROUP_OFFSET(2) + 6)
|
||||
#define NPCM_CLOCK_PWM_H (NPCM_CLOCK_GROUP_OFFSET(2) + 7)
|
||||
#define NPCM_CLOCK_SMB1 (NPCM_CLOCK_GROUP_OFFSET(3) + 0)
|
||||
#define NPCM_CLOCK_SMB2 (NPCM_CLOCK_GROUP_OFFSET(3) + 1)
|
||||
#define NPCM_CLOCK_SMB3 (NPCM_CLOCK_GROUP_OFFSET(3) + 2)
|
||||
#define NPCM_CLOCK_SMB4 (NPCM_CLOCK_GROUP_OFFSET(3) + 3)
|
||||
#define NPCM_CLOCK_SMB5 (NPCM_CLOCK_GROUP_OFFSET(3) + 4)
|
||||
#define NPCM_CLOCK_SMB6 (NPCM_CLOCK_GROUP_OFFSET(3) + 5)
|
||||
#define NPCM_CLOCK_GDMA (NPCM_CLOCK_GROUP_OFFSET(3) + 7)
|
||||
#define NPCM_CLOCK_ITIM1 (NPCM_CLOCK_GROUP_OFFSET(4) + 0)
|
||||
#define NPCM_CLOCK_ITIM2 (NPCM_CLOCK_GROUP_OFFSET(4) + 1)
|
||||
#define NPCM_CLOCK_ITIM3 (NPCM_CLOCK_GROUP_OFFSET(4) + 2)
|
||||
#define NPCM_CLOCK_SMB_DMA (NPCM_CLOCK_GROUP_OFFSET(4) + 3)
|
||||
#define NPCM_CLOCK_ADC (NPCM_CLOCK_GROUP_OFFSET(4) + 4)
|
||||
#define NPCM_CLOCK_PECI (NPCM_CLOCK_GROUP_OFFSET(4) + 5)
|
||||
#define NPCM_CLOCK_SPIP1 (NPCM_CLOCK_GROUP_OFFSET(4) + 7)
|
||||
#define NPCM_CLOCK_UART4 (NPCM_CLOCK_GROUP_OFFSET(5) + 0)
|
||||
#define NPCM_CLOCK_C2HACC (NPCM_CLOCK_GROUP_OFFSET(5) + 3)
|
||||
#define NPCM_CLOCK_SHM_REG (NPCM_CLOCK_GROUP_OFFSET(5) + 4)
|
||||
#define NPCM_CLOCK_SHM (NPCM_CLOCK_GROUP_OFFSET(5) + 5)
|
||||
#define NPCM_CLOCK_DP80 (NPCM_CLOCK_GROUP_OFFSET(5) + 6)
|
||||
#define NPCM_CLOCK_MSWC (NPCM_CLOCK_GROUP_OFFSET(5) + 7)
|
||||
#define NPCM_CLOCK_ITIM4 (NPCM_CLOCK_GROUP_OFFSET(6) + 0)
|
||||
#define NPCM_CLOCK_ITIM5 (NPCM_CLOCK_GROUP_OFFSET(6) + 1)
|
||||
#define NPCM_CLOCK_ITIM6 (NPCM_CLOCK_GROUP_OFFSET(6) + 2)
|
||||
#define NPCM_CLOCK_RNG (NPCM_CLOCK_GROUP_OFFSET(6) + 3)
|
||||
#define NPCM_CLOCK_SHA (NPCM_CLOCK_GROUP_OFFSET(6) + 5)
|
||||
#define NPCM_CLOCK_ESPI (NPCM_CLOCK_GROUP_OFFSET(6) + 7)
|
||||
#define NPCM_CLOCK_SMB7 (NPCM_CLOCK_GROUP_OFFSET(7) + 0)
|
||||
#define NPCM_CLOCK_SMB8 (NPCM_CLOCK_GROUP_OFFSET(7) + 1)
|
||||
#define NPCM_CLOCK_SMB9 (NPCM_CLOCK_GROUP_OFFSET(7) + 2)
|
||||
#define NPCM_CLOCK_SMB10 (NPCM_CLOCK_GROUP_OFFSET(7) + 3)
|
||||
#define NPCM_CLOCK_SMB11 (NPCM_CLOCK_GROUP_OFFSET(7) + 4)
|
||||
#define NPCM_CLOCK_SMB12 (NPCM_CLOCK_GROUP_OFFSET(7) + 5)
|
||||
#define NPCM_CLOCK_SIOX2 (NPCM_CLOCK_GROUP_OFFSET(7) + 6)
|
||||
#define NPCM_CLOCK_SIOX1 (NPCM_CLOCK_GROUP_OFFSET(7) + 7)
|
||||
#define NPCM_CLOCK_I3CI2 (NPCM_CLOCK_GROUP_OFFSET(8) + 0)
|
||||
#define NPCM_CLOCK_I3CI3 (NPCM_CLOCK_GROUP_OFFSET(8) + 1)
|
||||
#define NPCM_CLOCK_I3CI4 (NPCM_CLOCK_GROUP_OFFSET(8) + 2)
|
||||
#define NPCM_CLOCK_I3CI5 (NPCM_CLOCK_GROUP_OFFSET(8) + 3)
|
||||
#define NPCM_CLOCK_I3CI6 (NPCM_CLOCK_GROUP_OFFSET(8) + 4)
|
||||
|
||||
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_NPCM_CLOCK_H_ */
|
||||
Loading…
Reference in New Issue