From bfa1e36789610895a532d527a5119415d9183372 Mon Sep 17 00:00:00 2001 From: James Chiang Date: Wed, 22 May 2024 19:39:21 -0700 Subject: [PATCH] drivers: clock_control: add npcm clock control driver Add npcm clock control driver. Signed-off-by: James Chiang Signed-off-by: Joseph Liu Signed-off-by: Alan Yang --- drivers/clock_control/CMakeLists.txt | 1 + drivers/clock_control/Kconfig | 2 + drivers/clock_control/Kconfig.npcm | 11 + drivers/clock_control/clock_control_npcm.c | 365 ++++++++++++++++++ include/zephyr/dt-bindings/clock/npcm_clock.h | 72 ++++ 5 files changed, 451 insertions(+) create mode 100644 drivers/clock_control/Kconfig.npcm create mode 100644 drivers/clock_control/clock_control_npcm.c create mode 100644 include/zephyr/dt-bindings/clock/npcm_clock.h diff --git a/drivers/clock_control/CMakeLists.txt b/drivers/clock_control/CMakeLists.txt index 79079867e5d..861ab48c13f 100644 --- a/drivers/clock_control/CMakeLists.txt +++ b/drivers/clock_control/CMakeLists.txt @@ -19,6 +19,7 @@ zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_MCUX_SCG clock_cont zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_MCUX_SCG_K4 clock_control_mcux_scg_k4.c) zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_MCUX_SIM clock_control_mcux_sim.c) zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_MCUX_SYSCON clock_control_mcux_syscon.c) +zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_NPCM clock_control_npcm.c) zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_NPCX clock_control_npcx.c) zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_NRF clock_control_nrf.c) zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_NRF_DRIVER_CALIBRATION nrf_clock_calibration.c) diff --git a/drivers/clock_control/Kconfig b/drivers/clock_control/Kconfig index ca4db637014..efae3e11941 100644 --- a/drivers/clock_control/Kconfig +++ b/drivers/clock_control/Kconfig @@ -50,6 +50,8 @@ source "drivers/clock_control/Kconfig.mcux_sim" source "drivers/clock_control/Kconfig.mcux_syscon" +source "drivers/clock_control/Kconfig.npcm" + source "drivers/clock_control/Kconfig.npcx" source "drivers/clock_control/Kconfig.rv32m1" diff --git a/drivers/clock_control/Kconfig.npcm b/drivers/clock_control/Kconfig.npcm new file mode 100644 index 00000000000..cdf96bfb02f --- /dev/null +++ b/drivers/clock_control/Kconfig.npcm @@ -0,0 +1,11 @@ +# NPCM Clock controller driver configuration options + +# Copyright (c) 2024 Nuvoton Technology Corporation. +# SPDX-License-Identifier: Apache-2.0 + +config CLOCK_CONTROL_NPCM + bool "NPCM clock controller driver" + default y + depends on DT_HAS_NUVOTON_NPCM_PCC_ENABLED + help + Enable support for NPCM clock controller driver. diff --git a/drivers/clock_control/clock_control_npcm.c b/drivers/clock_control/clock_control_npcm.c new file mode 100644 index 00000000000..ffe1ba8b479 --- /dev/null +++ b/drivers/clock_control/clock_control_npcm.c @@ -0,0 +1,365 @@ +/* + * Copyright (c) 2024 Nuvoton Technology Corporation. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#define DT_DRV_COMPAT nuvoton_npcm_pcc + +#include +#include +#include + +#include +LOG_MODULE_REGISTER(clock_control_npcm, LOG_LEVEL_ERR); + +/* Driver config */ +struct npcm_pcc_config { + /* cdcg device base address */ + uintptr_t base_cdcg; + /* pmc device base address */ + uintptr_t base_pmc; +}; + +/* + * Core Domain Clock Generator (CDCG) device registers + */ +struct cdcg_reg { + /* High Frequency Clock Generator (HFCG) registers */ + /* 0x000: HFCG Control */ + volatile uint8_t hfcgctrl; + volatile uint8_t reserved1; + /* 0x002: HFCG M Low Byte Value */ + volatile uint8_t hfcgml; + volatile uint8_t reserved2; + /* 0x004: HFCG M High Byte Value */ + volatile uint8_t hfcgmh; + volatile uint8_t reserved3; + /* 0x006: HFCG N Value */ + volatile uint8_t hfcgn; + volatile uint8_t reserved4; + /* 0x008: HFCG Prescaler */ + volatile uint8_t hfcgp; + volatile uint8_t reserved5[7]; + /* 0x010: HFCG Bus Clock Dividers */ + volatile uint8_t hfcbcd; + volatile uint8_t reserved6; + /* 0x012: HFCG Bus Clock Dividers */ + volatile uint8_t hfcbcd1; + volatile uint8_t reserved7; + /* 0x014: HFCG Bus Clock Dividers */ + volatile uint8_t hfcbcd2; + volatile uint8_t reserved12[8]; + /* 0x01d: HFCG Bus Clock Dividers */ + volatile uint8_t hfcbcd3; +}; + +/* clock bus references */ +#define NPCM_CLOCK_BUS_LFCLK 0 +#define NPCM_CLOCK_BUS_OSC 1 +#define NPCM_CLOCK_BUS_FIU 2 +#define NPCM_CLOCK_BUS_I3C 3 +#define NPCM_CLOCK_BUS_CORE 4 +#define NPCM_CLOCK_BUS_APB1 5 +#define NPCM_CLOCK_BUS_APB2 6 +#define NPCM_CLOCK_BUS_APB3 7 +#define NPCM_CLOCK_BUS_APB4 8 +#define NPCM_CLOCK_BUS_AHB6 9 +#define NPCM_CLOCK_BUS_FMCLK 10 +#define NPCM_CLOCK_BUS_USB20_CLK 11 +#define NPCM_CLOCK_BUS_SIO_CLK 12 + +/* clock enable/disable references */ +#define NPCM_PWDWN_CTL0 0 +#define NPCM_PWDWN_CTL1 1 +#define NPCM_PWDWN_CTL2 2 +#define NPCM_PWDWN_CTL3 3 +#define NPCM_PWDWN_CTL4 4 +#define NPCM_PWDWN_CTL5 5 +#define NPCM_PWDWN_CTL6 6 +#define NPCM_PWDWN_CTL7 7 + +/* CDCG register fields */ +#define NPCM_HFCGCTRL_LOAD 0 +#define NPCM_HFCGCTRL_LOCK 2 +#define NPCM_HFCGCTRL_CLK_CHNG 7 + +/* Clock settings from pcc node */ +/* Target OFMCLK freq */ +#define OFMCLK DT_PROP(DT_NODELABEL(pcc), clock_frequency) +/* Core clock prescaler */ +#define FPRED_VAL (DT_PROP(DT_NODELABEL(pcc), core_prescaler) - 1) +/* APB1 clock divider */ +#define APB1DIV_VAL (DT_PROP(DT_NODELABEL(pcc), apb1_prescaler) - 1) +/* APB2 clock divider */ +#define APB2DIV_VAL (DT_PROP(DT_NODELABEL(pcc), apb2_prescaler) - 1) +/* APB3 clock divider */ +#define APB3DIV_VAL (DT_PROP(DT_NODELABEL(pcc), apb3_prescaler) - 1) +/* AHB6 clock divider*/ +#define AHB6DIV_VAL (DT_PROP(DT_NODELABEL(pcc), ahb6_prescaler) - 1) +/* FIU clock divider */ +#define FIUDIV_VAL (DT_PROP(DT_NODELABEL(pcc), fiu_prescaler) - 1) +/* I3C clock divider */ +#define I3CDIV_VAL (DT_PROP(DT_NODELABEL(pcc), i3c_prescaler) - 1) + +/* Core domain clock */ +#define CORE_CLK (OFMCLK / DT_PROP(DT_NODELABEL(pcc), core_prescaler)) +/* Low Frequency clock */ +#define LFCLK 32768 +/* FMUL clock */ +#define FMCLK OFMCLK /* FMUL clock = OFMCLK */ +/* APBs source clock */ +#define APBSRC_CLK OFMCLK +/* USB2.0 clock */ +#define USB20_CLK 12000000 +/* SIO clock */ +#define SIO_CLK 48000000 +/* Get APB clock freq */ +#define NPCM_APB_CLOCK(no) (APBSRC_CLK / (APB##no##DIV_VAL + 1)) + +struct freq_multiplier_t { + uint32_t ofmclk; + uint8_t hfcgn; + uint8_t hfcgmh; + uint8_t hfcgml; +}; + +static struct freq_multiplier_t freq_multiplier[] = { + {.ofmclk = 100000000, .hfcgn = 0x82, .hfcgmh = 0x0B, .hfcgml = 0xEC}, + {.ofmclk = 96000000, .hfcgn = 0x82, .hfcgmh = 0x0B, .hfcgml = 0x72}, + {.ofmclk = 80000000, .hfcgn = 0x82, .hfcgmh = 0x09, .hfcgml = 0x89}, + {.ofmclk = 66000000, .hfcgn = 0x82, .hfcgmh = 0x07, .hfcgml = 0xDE}, + {.ofmclk = 50000000, .hfcgn = 0x02, .hfcgmh = 0x0B, .hfcgml = 0xEC}, + {.ofmclk = 48000000, .hfcgn = 0x02, .hfcgmh = 0x0B, .hfcgml = 0x72}, + {.ofmclk = 40000000, .hfcgn = 0x02, .hfcgmh = 0x09, .hfcgml = 0x89}, + {.ofmclk = 33000000, .hfcgn = 0x02, .hfcgmh = 0x07, .hfcgml = 0xDE}}; + +struct clk_cfg_t { + uint32_t clock_id; + uint16_t bus; +}; + +static struct clk_cfg_t clk_cfg[] = { + {.clock_id = NPCM_CLOCK_PWM_I, .bus = NPCM_CLOCK_BUS_LFCLK}, + {.clock_id = NPCM_CLOCK_PWM_J, .bus = NPCM_CLOCK_BUS_LFCLK}, + {.clock_id = NPCM_CLOCK_I3CI, .bus = NPCM_CLOCK_BUS_APB3}, + {.clock_id = NPCM_CLOCK_UART3, .bus = NPCM_CLOCK_BUS_APB2}, + {.clock_id = NPCM_CLOCK_UART2, .bus = NPCM_CLOCK_BUS_APB2}, + + {.clock_id = NPCM_CLOCK_FIU, .bus = NPCM_CLOCK_BUS_FIU}, + {.clock_id = NPCM_CLOCK_USB20, .bus = NPCM_CLOCK_BUS_USB20_CLK}, + {.clock_id = NPCM_CLOCK_UART, .bus = NPCM_CLOCK_BUS_APB2}, + + {.clock_id = NPCM_CLOCK_PWM_A, .bus = NPCM_CLOCK_BUS_LFCLK}, + {.clock_id = NPCM_CLOCK_PWM_B, .bus = NPCM_CLOCK_BUS_LFCLK}, + {.clock_id = NPCM_CLOCK_PWM_C, .bus = NPCM_CLOCK_BUS_LFCLK}, + {.clock_id = NPCM_CLOCK_PWM_D, .bus = NPCM_CLOCK_BUS_LFCLK}, + {.clock_id = NPCM_CLOCK_PWM_E, .bus = NPCM_CLOCK_BUS_LFCLK}, + {.clock_id = NPCM_CLOCK_PWM_F, .bus = NPCM_CLOCK_BUS_LFCLK}, + {.clock_id = NPCM_CLOCK_PWM_G, .bus = NPCM_CLOCK_BUS_LFCLK}, + {.clock_id = NPCM_CLOCK_PWM_H, .bus = NPCM_CLOCK_BUS_LFCLK}, + + {.clock_id = NPCM_CLOCK_SMB1, .bus = NPCM_CLOCK_BUS_APB3}, + {.clock_id = NPCM_CLOCK_SMB2, .bus = NPCM_CLOCK_BUS_APB3}, + {.clock_id = NPCM_CLOCK_SMB3, .bus = NPCM_CLOCK_BUS_APB3}, + {.clock_id = NPCM_CLOCK_SMB4, .bus = NPCM_CLOCK_BUS_APB3}, + {.clock_id = NPCM_CLOCK_SMB5, .bus = NPCM_CLOCK_BUS_APB3}, + {.clock_id = NPCM_CLOCK_SMB6, .bus = NPCM_CLOCK_BUS_APB3}, + + {.clock_id = NPCM_CLOCK_ITIM1, .bus = NPCM_CLOCK_BUS_LFCLK}, + {.clock_id = NPCM_CLOCK_ITIM2, .bus = NPCM_CLOCK_BUS_LFCLK}, + {.clock_id = NPCM_CLOCK_ITIM3, .bus = NPCM_CLOCK_BUS_LFCLK}, + {.clock_id = NPCM_CLOCK_ADC, .bus = NPCM_CLOCK_BUS_APB1}, + {.clock_id = NPCM_CLOCK_PECI, .bus = NPCM_CLOCK_BUS_FMCLK}, + + {.clock_id = NPCM_CLOCK_UART4, .bus = NPCM_CLOCK_BUS_APB2}, + + {.clock_id = NPCM_CLOCK_ESPI, .bus = NPCM_CLOCK_BUS_APB3}, + + {.clock_id = NPCM_CLOCK_SMB7, .bus = NPCM_CLOCK_BUS_APB3}, + {.clock_id = NPCM_CLOCK_SMB8, .bus = NPCM_CLOCK_BUS_APB3}, + {.clock_id = NPCM_CLOCK_SMB9, .bus = NPCM_CLOCK_BUS_APB3}, + {.clock_id = NPCM_CLOCK_SMB10, .bus = NPCM_CLOCK_BUS_APB3}, + {.clock_id = NPCM_CLOCK_SMB11, .bus = NPCM_CLOCK_BUS_APB3}, + {.clock_id = NPCM_CLOCK_SMB12, .bus = NPCM_CLOCK_BUS_APB3}, +}; + +/* PMC multi-registers */ +#define NPCM_PWDWN_CTL_OFFSET(n) (((n) < 7) ? (0x07 + n) : (0x15 + (n - 7))) +#define NPCM_PWDWN_CTL(base, n) (*(volatile uint8_t *)(base + NPCM_PWDWN_CTL_OFFSET(n))) +#define NPCM_CLOCK_REG_OFFSET(n) ((n) >> 3) +#define NPCM_CLOCK_REG_BIT_OFFSET(n) ((n) & 0x7) + +#define DRV_CONFIG(dev) ((const struct npcm_pcc_config *)(dev)->config) + +/* Clock controller local functions */ +static struct clk_cfg_t *npcm_get_cfg(clock_control_subsys_t sub_system) +{ + uint32_t clk_id = (uint32_t)sub_system; + uint32_t i; + + for (i = 0; i < ARRAY_SIZE(clk_cfg); i++) { + if (clk_cfg[i].clock_id == clk_id) { + return &clk_cfg[i]; + } + } + + return NULL; +} + +static inline int npcm_clock_control_on(const struct device *dev, clock_control_subsys_t sub_system) +{ + uint32_t clk_id = (uint32_t)sub_system; + struct clk_cfg_t *priv; + const uint32_t pmc_base = DRV_CONFIG(dev)->base_pmc; + + priv = npcm_get_cfg(sub_system); + if (!priv) { + LOG_ERR("Unsupported clock id %d", clk_id); + return -EINVAL; + } + + /* Clear related PD (Power-Down) bit of module to turn on clock */ + NPCM_PWDWN_CTL(pmc_base, NPCM_CLOCK_REG_OFFSET(priv->clock_id)) &= + ~(BIT(NPCM_CLOCK_REG_BIT_OFFSET(priv->clock_id))); + return 0; +} + +static inline int npcm_clock_control_off(const struct device *dev, + clock_control_subsys_t sub_system) +{ + uint32_t clk_id = (uint32_t)sub_system; + struct clk_cfg_t *priv; + const uint32_t pmc_base = DRV_CONFIG(dev)->base_pmc; + + priv = npcm_get_cfg(sub_system); + if (!priv) { + LOG_ERR("Unsupported clock id %d", clk_id); + return -EINVAL; + } + + /* Set related PD (Power-Down) bit of module to turn off clock */ + NPCM_PWDWN_CTL(pmc_base, NPCM_CLOCK_REG_OFFSET(priv->clock_id)) |= + ~(BIT(NPCM_CLOCK_REG_BIT_OFFSET(priv->clock_id))); + return 0; +} + +static int npcm_clock_control_get_subsys_rate(const struct device *dev, + clock_control_subsys_t sub_system, uint32_t *rate) +{ + ARG_UNUSED(dev); + uint32_t clk_id = (uint32_t)sub_system; + struct clk_cfg_t *priv; + + priv = npcm_get_cfg(sub_system); + if (!priv) { + LOG_ERR("Unsupported clock id %d", clk_id); + return -EINVAL; + } + + switch (priv->bus) { + case NPCM_CLOCK_BUS_APB1: + *rate = NPCM_APB_CLOCK(1); + break; + case NPCM_CLOCK_BUS_APB2: + *rate = NPCM_APB_CLOCK(2); + break; + case NPCM_CLOCK_BUS_APB3: + *rate = NPCM_APB_CLOCK(3); + break; + case NPCM_CLOCK_BUS_AHB6: + *rate = CORE_CLK / (AHB6DIV_VAL + 1); + break; + case NPCM_CLOCK_BUS_FIU: + *rate = CORE_CLK / (FIUDIV_VAL + 1); + break; + case NPCM_CLOCK_BUS_I3C: + *rate = CORE_CLK / (I3CDIV_VAL + 1); + break; + case NPCM_CLOCK_BUS_CORE: + *rate = CORE_CLK; + break; + case NPCM_CLOCK_BUS_LFCLK: + *rate = LFCLK; + break; + case NPCM_CLOCK_BUS_FMCLK: + *rate = FMCLK; + break; + case NPCM_CLOCK_BUS_USB20_CLK: + *rate = USB20_CLK; + break; + case NPCM_CLOCK_BUS_SIO_CLK: + *rate = SIO_CLK; + break; + default: + *rate = 0U; + /* Invalid parameters */ + return -EINVAL; + } + + return 0; +} + +/* Clock controller driver registration */ +static struct clock_control_driver_api npcm_clock_control_api = { + .on = npcm_clock_control_on, + .off = npcm_clock_control_off, + .get_rate = npcm_clock_control_get_subsys_rate, +}; + +static int npcm_clock_control_init(const struct device *dev) +{ + struct cdcg_reg *const priv = (struct cdcg_reg *)(DRV_CONFIG(dev)->base_cdcg); + struct freq_multiplier_t *freq_p; + int i; + + for (i = 0; i < ARRAY_SIZE(freq_multiplier); i++) { + if (freq_multiplier[i].ofmclk == OFMCLK) { + freq_p = &freq_multiplier[i]; + break; + } + } + + if (i >= ARRAY_SIZE(freq_multiplier)) { + LOG_ERR("Unsupported OFMCLK frequency %d", OFMCLK); + return -EINVAL; + } + + /* + * Resetting the OFMCLK (even to the same value) will make the clock + * unstable for a little which can affect peripheral communication like + * eSPI. Skip this if not needed. + */ + if (priv->hfcgn != freq_p->hfcgn || priv->hfcgml != freq_p->hfcgml || + priv->hfcgmh != freq_p->hfcgmh) { + /* + * Configure frequency multiplier M/N values according to + * the requested OFMCLK (Unit:Hz). + */ + priv->hfcgn = freq_p->hfcgn; + priv->hfcgml = freq_p->hfcgml; + priv->hfcgmh = freq_p->hfcgmh; + + /* Load M and N values into the frequency multiplier */ + priv->hfcgctrl |= BIT(NPCM_HFCGCTRL_LOAD); + /* Wait for stable */ + while (sys_test_bit(priv->hfcgctrl, NPCM_HFCGCTRL_CLK_CHNG)) + ; + } + + /* Set all clock prescalers of core and peripherals. */ + priv->hfcgp = (FPRED_VAL << 4) | AHB6DIV_VAL; + priv->hfcbcd = APB1DIV_VAL | (APB2DIV_VAL << 4); + priv->hfcbcd1 = (I3CDIV_VAL << 2) | FIUDIV_VAL; + priv->hfcbcd2 = APB3DIV_VAL; + + return 0; +} + +const struct npcm_pcc_config pcc_config = { + .base_cdcg = DT_INST_REG_ADDR_BY_NAME(0, cdcg), + .base_pmc = DT_INST_REG_ADDR_BY_NAME(0, pmc), +}; + +DEVICE_DT_INST_DEFINE(0, &npcm_clock_control_init, NULL, NULL, &pcc_config, PRE_KERNEL_1, + CONFIG_KERNEL_INIT_PRIORITY_OBJECTS, &npcm_clock_control_api); diff --git a/include/zephyr/dt-bindings/clock/npcm_clock.h b/include/zephyr/dt-bindings/clock/npcm_clock.h new file mode 100644 index 00000000000..d4a1b0c374a --- /dev/null +++ b/include/zephyr/dt-bindings/clock/npcm_clock.h @@ -0,0 +1,72 @@ +/* + * Copyright (c) 2024 Nuvoton Technology Corporation. + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_NPCM_CLOCK_H_ +#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_NPCM_CLOCK_H_ + +/* clock bus references */ +#define NPCM_CLOCK_GROUP_OFFSET(N) ((N) << 3) + +#define NPCM_CLOCK_PWM_I (NPCM_CLOCK_GROUP_OFFSET(0) + 0) +#define NPCM_CLOCK_PWM_J (NPCM_CLOCK_GROUP_OFFSET(0) + 1) +#define NPCM_CLOCK_I3CI (NPCM_CLOCK_GROUP_OFFSET(0) + 2) +#define NPCM_CLOCK_UART3 (NPCM_CLOCK_GROUP_OFFSET(0) + 5) +#define NPCM_CLOCK_UART2 (NPCM_CLOCK_GROUP_OFFSET(0) + 6) +#define NPCM_CLOCK_SPIM (NPCM_CLOCK_GROUP_OFFSET(1) + 0) +#define NPCM_CLOCK_FIU (NPCM_CLOCK_GROUP_OFFSET(1) + 2) +#define NPCM_CLOCK_USB20 (NPCM_CLOCK_GROUP_OFFSET(1) + 3) +#define NPCM_CLOCK_UART (NPCM_CLOCK_GROUP_OFFSET(1) + 4) +#define NPCM_CLOCK_MFT1 (NPCM_CLOCK_GROUP_OFFSET(1) + 5) +#define NPCM_CLOCK_MFT2 (NPCM_CLOCK_GROUP_OFFSET(1) + 6) +#define NPCM_CLOCK_MFT3 (NPCM_CLOCK_GROUP_OFFSET(1) + 7) +#define NPCM_CLOCK_PWM_A (NPCM_CLOCK_GROUP_OFFSET(2) + 0) +#define NPCM_CLOCK_PWM_B (NPCM_CLOCK_GROUP_OFFSET(2) + 1) +#define NPCM_CLOCK_PWM_C (NPCM_CLOCK_GROUP_OFFSET(2) + 2) +#define NPCM_CLOCK_PWM_D (NPCM_CLOCK_GROUP_OFFSET(2) + 3) +#define NPCM_CLOCK_PWM_E (NPCM_CLOCK_GROUP_OFFSET(2) + 4) +#define NPCM_CLOCK_PWM_F (NPCM_CLOCK_GROUP_OFFSET(2) + 5) +#define NPCM_CLOCK_PWM_G (NPCM_CLOCK_GROUP_OFFSET(2) + 6) +#define NPCM_CLOCK_PWM_H (NPCM_CLOCK_GROUP_OFFSET(2) + 7) +#define NPCM_CLOCK_SMB1 (NPCM_CLOCK_GROUP_OFFSET(3) + 0) +#define NPCM_CLOCK_SMB2 (NPCM_CLOCK_GROUP_OFFSET(3) + 1) +#define NPCM_CLOCK_SMB3 (NPCM_CLOCK_GROUP_OFFSET(3) + 2) +#define NPCM_CLOCK_SMB4 (NPCM_CLOCK_GROUP_OFFSET(3) + 3) +#define NPCM_CLOCK_SMB5 (NPCM_CLOCK_GROUP_OFFSET(3) + 4) +#define NPCM_CLOCK_SMB6 (NPCM_CLOCK_GROUP_OFFSET(3) + 5) +#define NPCM_CLOCK_GDMA (NPCM_CLOCK_GROUP_OFFSET(3) + 7) +#define NPCM_CLOCK_ITIM1 (NPCM_CLOCK_GROUP_OFFSET(4) + 0) +#define NPCM_CLOCK_ITIM2 (NPCM_CLOCK_GROUP_OFFSET(4) + 1) +#define NPCM_CLOCK_ITIM3 (NPCM_CLOCK_GROUP_OFFSET(4) + 2) +#define NPCM_CLOCK_SMB_DMA (NPCM_CLOCK_GROUP_OFFSET(4) + 3) +#define NPCM_CLOCK_ADC (NPCM_CLOCK_GROUP_OFFSET(4) + 4) +#define NPCM_CLOCK_PECI (NPCM_CLOCK_GROUP_OFFSET(4) + 5) +#define NPCM_CLOCK_SPIP1 (NPCM_CLOCK_GROUP_OFFSET(4) + 7) +#define NPCM_CLOCK_UART4 (NPCM_CLOCK_GROUP_OFFSET(5) + 0) +#define NPCM_CLOCK_C2HACC (NPCM_CLOCK_GROUP_OFFSET(5) + 3) +#define NPCM_CLOCK_SHM_REG (NPCM_CLOCK_GROUP_OFFSET(5) + 4) +#define NPCM_CLOCK_SHM (NPCM_CLOCK_GROUP_OFFSET(5) + 5) +#define NPCM_CLOCK_DP80 (NPCM_CLOCK_GROUP_OFFSET(5) + 6) +#define NPCM_CLOCK_MSWC (NPCM_CLOCK_GROUP_OFFSET(5) + 7) +#define NPCM_CLOCK_ITIM4 (NPCM_CLOCK_GROUP_OFFSET(6) + 0) +#define NPCM_CLOCK_ITIM5 (NPCM_CLOCK_GROUP_OFFSET(6) + 1) +#define NPCM_CLOCK_ITIM6 (NPCM_CLOCK_GROUP_OFFSET(6) + 2) +#define NPCM_CLOCK_RNG (NPCM_CLOCK_GROUP_OFFSET(6) + 3) +#define NPCM_CLOCK_SHA (NPCM_CLOCK_GROUP_OFFSET(6) + 5) +#define NPCM_CLOCK_ESPI (NPCM_CLOCK_GROUP_OFFSET(6) + 7) +#define NPCM_CLOCK_SMB7 (NPCM_CLOCK_GROUP_OFFSET(7) + 0) +#define NPCM_CLOCK_SMB8 (NPCM_CLOCK_GROUP_OFFSET(7) + 1) +#define NPCM_CLOCK_SMB9 (NPCM_CLOCK_GROUP_OFFSET(7) + 2) +#define NPCM_CLOCK_SMB10 (NPCM_CLOCK_GROUP_OFFSET(7) + 3) +#define NPCM_CLOCK_SMB11 (NPCM_CLOCK_GROUP_OFFSET(7) + 4) +#define NPCM_CLOCK_SMB12 (NPCM_CLOCK_GROUP_OFFSET(7) + 5) +#define NPCM_CLOCK_SIOX2 (NPCM_CLOCK_GROUP_OFFSET(7) + 6) +#define NPCM_CLOCK_SIOX1 (NPCM_CLOCK_GROUP_OFFSET(7) + 7) +#define NPCM_CLOCK_I3CI2 (NPCM_CLOCK_GROUP_OFFSET(8) + 0) +#define NPCM_CLOCK_I3CI3 (NPCM_CLOCK_GROUP_OFFSET(8) + 1) +#define NPCM_CLOCK_I3CI4 (NPCM_CLOCK_GROUP_OFFSET(8) + 2) +#define NPCM_CLOCK_I3CI5 (NPCM_CLOCK_GROUP_OFFSET(8) + 3) +#define NPCM_CLOCK_I3CI6 (NPCM_CLOCK_GROUP_OFFSET(8) + 4) + +#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_NPCM_CLOCK_H_ */