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arch: riscv: fix exception_depth with RISCV_ALWAYS_SWITCH_THROUGH_ECALL 

When 'arch_switch()' switches though Ecall, 'exception_depth' is
incorrectly added to the next thread because the current thread is updated
before arch_switch().
Add 'exception_depth' back to the previous thread when Ecall is called from
'arch_switch()'.

Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
This commit is contained in:
Jimmy Zheng 2024-07-05 10:11:32 +08:00 committed by Anas Nashif
parent 89f3d220d4
commit ba263da94e
1 changed files with 16 additions and 0 deletions
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16
arch/riscv/core/isr.S
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@ -398,6 +398,22 @@ is_kernel_syscall:
bne t0, t1, skip_schedule
lr a0, __struct_arch_esf_a0_OFFSET(sp)
lr a1, __struct_arch_esf_a1_OFFSET(sp)
#ifdef CONFIG_FPU_SHARING
/*
* When an ECALL is used for a context-switch, the current thread has
* been updated to the next thread.
* Add the exception_depth back to the previous thread.
*/
lb t1, _thread_offset_to_exception_depth(a0)
add t1, t1, -1
sb t1, _thread_offset_to_exception_depth(a0)
lb t1, _thread_offset_to_exception_depth(a1)
add t1, t1, 1
sb t1, _thread_offset_to_exception_depth(a1)
#endif
j reschedule
skip_schedule:
#endif