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soc: arc: define ICI in DT 

ICI (Inter-Core Interrupt Unit) interrupts and priorities were hardcoded
in C files. This patch moves this information to Devicetree and updates
code to make use of it.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
This commit is contained in:
Gerard Marull-Paretas 2022-06-15 16:34:01 +02:00 committed by Anas Nashif
parent 60d3e487a3
commit b2a1eeb6ac
8 changed files with 38 additions and 20 deletions
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20
arch/arc/core/arc_smp.c
View File

@ -13,16 +13,8 @@
#include <zephyr/kernel.h>
#include <zephyr/kernel_structs.h>
#include <ksched.h>
#include <soc.h>
#include <zephyr/init.h>
#ifndef IRQ_ICI
#define IRQ_ICI 19
#endif
#define ARCV2_ICI_IRQ_PRIORITY 1
#define MP_PRIMARY_CPU_ID 0
volatile struct {
@ -112,8 +104,9 @@ void z_arc_slave_start(int cpu_num)
z_irq_setup();
z_arc_connect_ici_clear();
z_irq_priority_set(IRQ_ICI, ARCV2_ICI_IRQ_PRIORITY, 0);
irq_enable(IRQ_ICI);
z_irq_priority_set(DT_IRQN(DT_NODELABEL(ici)),
DT_IRQ(DT_NODELABEL(ici), priority), 0);
irq_enable(DT_IRQN(DT_NODELABEL(ici)));
#endif
/* call the function set by arch_start_cpu */
fn = arc_cpu_init[cpu_num].fn;
@ -162,10 +155,11 @@ static int arc_smp_init(const struct device *dev)
if (bcr.ipi) {
/* register ici interrupt, just need master core to register once */
z_arc_connect_ici_clear();
IRQ_CONNECT(IRQ_ICI, ARCV2_ICI_IRQ_PRIORITY,
sched_ipi_handler, NULL, 0);
IRQ_CONNECT(DT_IRQN(DT_NODELABEL(ici)),
DT_IRQ(DT_NODELABEL(ici), priority),
sched_ipi_handler, NULL, 0);
irq_enable(IRQ_ICI);
irq_enable(DT_IRQN(DT_NODELABEL(ici)));
} else {
__ASSERT(0,
"ARC connect has no inter-core interrupt\n");

14
boards/arc/nsim/nsim-smp.dtsi Normal file
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@ -0,0 +1,14 @@
/*
* Copyright (c) 2022 Nordic Semiconductor ASA
* SPDX-License-Identifier: Apache-2.0
*/
#include "nsim.dtsi"
/ {
ici: intercore-interrupt-unit {
compatible = "snps,archs-ici";
interrupts = <19 1>;
interrupt-parent = <&intc>;
};
};

2
boards/arc/nsim/nsim_hs5x_smp.dts
View File

@ -6,7 +6,7 @@
/dts-v1/;
#include "nsim.dtsi"
#include "nsim-smp.dtsi"
#include "nsim-flat-mem.dtsi"
/ {

2
boards/arc/nsim/nsim_hs6x_smp.dts
View File

@ -6,7 +6,7 @@
/dts-v1/;
#include "nsim.dtsi"
#include "nsim-smp.dtsi"
#include "nsim-flat-mem.dtsi"
/ {

2
boards/arc/nsim/nsim_hs_smp.dts
View File

@ -6,7 +6,7 @@
/dts-v1/;
#include "nsim.dtsi"
#include "nsim-smp.dtsi"
#include "nsim-flat-mem.dtsi"
/ {

6
dts/arc/synopsys/arc_hsdk.dtsi
View File

@ -54,6 +54,12 @@
interrupt-parent = <&intc>;
};
ici: intercore-interrupt-unit {
compatible = "snps,archs-ici";
interrupts = <19 1>;
interrupt-parent = <&intc>;
};
timer0: timer0 {
compatible = "snps,arc-timer";
interrupts = <16 1>;

8
dts/bindings/misc/snps,archs-ici.yaml Normal file
View File

@ -0,0 +1,8 @@
# Copyright (c) 2022 Nordic Semiconductor ASA
# SPDX-License-Identifier: Apache-2.0
description: Inter-Core Interrupt Unit (ICI)
compatible: "snps,archs-ici"
include: base.yaml

4
soc/arc/snps_arc_hsdk/soc.h
View File

@ -16,10 +16,6 @@
#include <zephyr/sys/util.h>
/* ARC HS Core IRQs */
#define IRQ_ICI 19
#ifndef _ASMLANGUAGE