soc: MCXW71: Add BLE support

- Add IMU regions
- Add HCI definition
- Add config when BT is enabled

Signed-off-by: Yassine El Aissaoui <yassine.elaissaoui@nxp.com>

dts/arm/nxp/nxp_mcxw71.dtsi

@@ -1,5 +1,5 @@
 /*
- * Copyright 2023 NXP
+ * Copyright 2023-2024 NXP
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -10,12 +10,17 @@
 #include <zephyr/dt-bindings/gpio/gpio.h>
 #include <zephyr/dt-bindings/pwm/pwm.h>
 #include <zephyr/dt-bindings/i2c/i2c.h>
+#include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
 
 / {
 	aliases {
 		watchdog0 = &wdog0;
 	};
 
+	chosen {
+		zephyr,bt-hci = &hci;
+	};
+
 	cpus {
 		#address-cells = <1>;
 		#size-cells = <0>;
@@ -64,8 +69,6 @@
 
 		smu2: sram@489c0000 {
 			ranges = <0x0 0x489c0000 DT_SIZE_K(40)>;
-			#address-cells = <1>;
-			#size-cells = <1>;
 		};
 
 		peripheral: peripheral@50000000 {
@@ -120,6 +123,18 @@
 	arm,num-irq-priority-bits = <3>;
 };
 
+&smu2 {
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	rpmsgmem: memory@8800 {
+		compatible = "zephyr,memory-region","mmio-sram";
+		reg = <0x8800 DT_SIZE_K(6)>;
+		zephyr,memory-region = "rpmsg_sh_mem";
+		zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM) )>;
+	};
+};
+
 &pbridge2 {
 	#address-cells = <1>;
 	#size-cells = <1>;
@@ -266,6 +281,12 @@
 		resolution = <32>;
 		status = "disabled";
 	};
+
+	hci: hci_ble {
+		compatible = "nxp,hci-ble";
+		interrupts = <48 2>;
+		interrupt-names = "hci_int";
+	};
 };
 
 &fast_peripheral0 {

soc/nxp/mcx/mcxw/CMakeLists.txt

@@ -1,4 +1,4 @@
-# Copyright 2023 NXP
+# Copyright 2023-2024 NXP
 #
 # SPDX-License-Identifier: Apache-2.0
 
@@ -7,3 +7,5 @@ zephyr_sources(soc.c mcxw71_platform_init.S)
 zephyr_include_directories(.)
 
 set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "")
+
+zephyr_linker_sources_ifdef(CONFIG_BT RAM_SECTIONS sections.ld)

soc/nxp/mcx/mcxw/Kconfig.defconfig

@@ -12,4 +12,20 @@ config SYS_CLOCK_HW_CYCLES_PER_SEC
 config MCUX_FLASH_K4_API
 	default y
 
+if BT
+
+# Include intercore messaging component
+config NXP_RF_IMU
+	default y
+
+#  Set the controller's public identity using NXP vendor command
+config BT_HCI_SET_PUBLIC_ADDR
+	default y
+
+# HCI RX buffers are received in ISR context. RX messages
+# need to be queued and processed by a dedicated thread
+config HCI_NXP_RX_THREAD
+	default y
+
+endif # BT
 endif # SOC_SERIES_MCXW

soc/nxp/mcx/mcxw/sections.ld

@@ -0,0 +1,18 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/* NOINIT section for rpmsg_sh_mem */
+.noinit_rpmsg_sh_mem (NOLOAD) : ALIGN(4)
+{
+   __RPMSG_SH_MEM_START__ = .;
+PROVIDE(rpmsg_sh_mem_start = __RPMSG_SH_MEM_START__);
+
+   *(.noinit.$rpmsg_sh_mem*)
+   . = ALIGN(4) ;
+   __RPMSG_SH_MEM_END__ = .;
+PROVIDE(rpmsg_sh_mem_end = __RPMSG_SH_MEM_END__);
+
+} > rpmsg_sh_mem

soc/nxp/mcx/mcxw/soc.h

@@ -1,5 +1,5 @@
 /*
- * Copyright 2023 NXP
+ * Copyright 2023-2024 NXP
  * SPDX-License-Identifier: Apache-2.0
  */
 
@@ -10,4 +10,6 @@
 
 #define PORT_MUX_GPIO kPORT_MuxAsGpio
 
+#define ble_hci_handler RF_IMU0_IRQHandler
+
 #endif /* _SOC__H_ */