From ad8b62413d1bfc421509fc1435f81cd9204f8eb1 Mon Sep 17 00:00:00 2001 From: Yassine El Aissaoui Date: Tue, 24 Sep 2024 15:02:56 +0200 Subject: [PATCH] soc: MCXW71: Add BLE support - Add IMU regions - Add HCI definition - Add config when BT is enabled Signed-off-by: Yassine El Aissaoui --- dts/arm/nxp/nxp_mcxw71.dtsi | 27 ++++++++++++++++++++++++--- soc/nxp/mcx/mcxw/CMakeLists.txt | 4 +++- soc/nxp/mcx/mcxw/Kconfig.defconfig | 16 ++++++++++++++++ soc/nxp/mcx/mcxw/sections.ld | 18 ++++++++++++++++++ soc/nxp/mcx/mcxw/soc.h | 4 +++- 5 files changed, 64 insertions(+), 5 deletions(-) create mode 100644 soc/nxp/mcx/mcxw/sections.ld diff --git a/dts/arm/nxp/nxp_mcxw71.dtsi b/dts/arm/nxp/nxp_mcxw71.dtsi index d5a684d08e4..49ecf822374 100644 --- a/dts/arm/nxp/nxp_mcxw71.dtsi +++ b/dts/arm/nxp/nxp_mcxw71.dtsi @@ -1,5 +1,5 @@ /* - * Copyright 2023 NXP + * Copyright 2023-2024 NXP * * SPDX-License-Identifier: Apache-2.0 */ @@ -10,12 +10,17 @@ #include #include #include +#include / { aliases { watchdog0 = &wdog0; }; + chosen { + zephyr,bt-hci = &hci; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -64,8 +69,6 @@ smu2: sram@489c0000 { ranges = <0x0 0x489c0000 DT_SIZE_K(40)>; - #address-cells = <1>; - #size-cells = <1>; }; peripheral: peripheral@50000000 { @@ -120,6 +123,18 @@ arm,num-irq-priority-bits = <3>; }; +&smu2 { + #address-cells = <1>; + #size-cells = <1>; + + rpmsgmem: memory@8800 { + compatible = "zephyr,memory-region","mmio-sram"; + reg = <0x8800 DT_SIZE_K(6)>; + zephyr,memory-region = "rpmsg_sh_mem"; + zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM) )>; + }; +}; + &pbridge2 { #address-cells = <1>; #size-cells = <1>; @@ -266,6 +281,12 @@ resolution = <32>; status = "disabled"; }; + + hci: hci_ble { + compatible = "nxp,hci-ble"; + interrupts = <48 2>; + interrupt-names = "hci_int"; + }; }; &fast_peripheral0 { diff --git a/soc/nxp/mcx/mcxw/CMakeLists.txt b/soc/nxp/mcx/mcxw/CMakeLists.txt index 47cef05f237..3447992547b 100644 --- a/soc/nxp/mcx/mcxw/CMakeLists.txt +++ b/soc/nxp/mcx/mcxw/CMakeLists.txt @@ -1,4 +1,4 @@ -# Copyright 2023 NXP +# Copyright 2023-2024 NXP # # SPDX-License-Identifier: Apache-2.0 @@ -7,3 +7,5 @@ zephyr_sources(soc.c mcxw71_platform_init.S) zephyr_include_directories(.) set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "") + +zephyr_linker_sources_ifdef(CONFIG_BT RAM_SECTIONS sections.ld) diff --git a/soc/nxp/mcx/mcxw/Kconfig.defconfig b/soc/nxp/mcx/mcxw/Kconfig.defconfig index 38c57f960f7..6a106466e67 100644 --- a/soc/nxp/mcx/mcxw/Kconfig.defconfig +++ b/soc/nxp/mcx/mcxw/Kconfig.defconfig @@ -12,4 +12,20 @@ config SYS_CLOCK_HW_CYCLES_PER_SEC config MCUX_FLASH_K4_API default y +if BT + +# Include intercore messaging component +config NXP_RF_IMU + default y + +# Set the controller's public identity using NXP vendor command +config BT_HCI_SET_PUBLIC_ADDR + default y + +# HCI RX buffers are received in ISR context. RX messages +# need to be queued and processed by a dedicated thread +config HCI_NXP_RX_THREAD + default y + +endif # BT endif # SOC_SERIES_MCXW diff --git a/soc/nxp/mcx/mcxw/sections.ld b/soc/nxp/mcx/mcxw/sections.ld new file mode 100644 index 00000000000..f4c2370e59f --- /dev/null +++ b/soc/nxp/mcx/mcxw/sections.ld @@ -0,0 +1,18 @@ +/* + * Copyright 2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* NOINIT section for rpmsg_sh_mem */ +.noinit_rpmsg_sh_mem (NOLOAD) : ALIGN(4) +{ + __RPMSG_SH_MEM_START__ = .; +PROVIDE(rpmsg_sh_mem_start = __RPMSG_SH_MEM_START__); + + *(.noinit.$rpmsg_sh_mem*) + . = ALIGN(4) ; + __RPMSG_SH_MEM_END__ = .; +PROVIDE(rpmsg_sh_mem_end = __RPMSG_SH_MEM_END__); + +} > rpmsg_sh_mem diff --git a/soc/nxp/mcx/mcxw/soc.h b/soc/nxp/mcx/mcxw/soc.h index bd6650d57c8..9d1de1abadc 100644 --- a/soc/nxp/mcx/mcxw/soc.h +++ b/soc/nxp/mcx/mcxw/soc.h @@ -1,5 +1,5 @@ /* - * Copyright 2023 NXP + * Copyright 2023-2024 NXP * SPDX-License-Identifier: Apache-2.0 */ @@ -10,4 +10,6 @@ #define PORT_MUX_GPIO kPORT_MuxAsGpio +#define ble_hci_handler RF_IMU0_IRQHandler + #endif /* _SOC__H_ */