arch/riscv: remove the `Kconfig.core` file

This commit removes the `Kconfig.core` file. It's been largely unused, and
the only symbol it provides (`RISCV_CORE_E31`) overlaps with the SoC-layer
provided `SOC_SERIES_SIFIVE_FREEDOM_FE300`.

As of date, the only SoC that uses the E31 core in Zephyr is the FE310 SoC.

Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>

arch/riscv/Kconfig

@@ -374,6 +374,5 @@ config ARCH_HAS_SINGLE_THREAD_SUPPORT
 	default y if !SMP
 
 rsource "Kconfig.isa"
-rsource "Kconfig.core"
 
 endmenu

arch/riscv/Kconfig.core

@@ -1,18 +0,0 @@
-# Copyright (c) 2022 Carlo Caione <ccaione@baylibre.com>
-# SPDX-License-Identifier: Apache-2.0
-
-menu "RISCV core"
-
-config RISCV_CORE_E31
-	bool "E31 core"
-	select RISCV_PMP
-	select RISCV_ISA_RV32I
-	select RISCV_ISA_EXT_M
-	select RISCV_ISA_EXT_A
-	select RISCV_ISA_EXT_C
-	select RISCV_ISA_EXT_ZICSR
-	select RISCV_ISA_EXT_ZIFENCEI
-	help
-	  SiFive E31 Standard Core
-
-endmenu

boards/qemu/riscv32_xip/qemu_riscv32_xip_defconfig

@@ -8,4 +8,3 @@ CONFIG_PINCTRL=y
 CONFIG_GPIO=y
 CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=10000000
 CONFIG_QEMU_ICOUNT_SHIFT=6
-CONFIG_RISCV_CORE_E31=y

boards/sifive/hifive1/Kconfig

@@ -1,5 +0,0 @@
-# Copyright (c) 2024 Antmicro <www.antmicro.com>
-# SPDX-License-Identifier: Apache-2.0
-
-config BOARD_HIFIVE1
-	select RISCV_CORE_E31

soc/sifive/sifive_freedom/fe300/Kconfig

@@ -9,9 +9,12 @@ config SOC_SERIES_SIFIVE_FREEDOM_FE300
 	select RISCV
 	select RISCV_PRIVILEGED
 	select RISCV_HAS_PLIC
+	select RISCV_PMP
+
 	select RISCV_ISA_RV32I
 	select RISCV_ISA_EXT_M
 	select RISCV_ISA_EXT_A
+	select RISCV_ISA_EXT_C
 	select RISCV_ISA_EXT_ZICSR
 	select RISCV_ISA_EXT_ZIFENCEI