dts: bindings: mbox: rename plic-sw to mbox-plic-sw

Renamed andestech,plic-sw to andestech,mbox-plic-sw because the mbox node
is based on the PLIC interrupt controller node instead using the plic
hardware directly.

Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>

boards/andestech/adp_xc7k_ae350/adp_xc7k_ae350.dts

@@ -215,3 +215,7 @@
 &dma0 {
 	status = "okay";
 };
+
+&mbox {
+	status = "okay";
+};

dts/bindings/mbox/andestech,mbox-plic-sw.yaml

@@ -5,20 +5,15 @@
 #
 
 description: |
-  This is a representation of AndesTech PLIC-SW node
+  This is a representation of AndesTech MBOX PLIC-SW node
 
-compatible: "andestech,plic-sw"
+compatible: "andestech,mbox-plic-sw"
 
 include: [base.yaml, mailbox-controller.yaml]
 
 properties:
-  reg:
+  interrupts:
     required: true
 
-  channel-max:
-    type: int
-    required: true
-    description: Supported channels max
-
 mbox-cells:
   - channel

dts/riscv/andes/andes_v5_ae350.dtsi

@@ -193,6 +193,25 @@
 					       &cpu6_intc 3 &cpu7_intc 3>;
 
 			#size-cells = <0>;
+			mbox: mbox-controller@0 {
+				compatible = "andestech,mbox-plic-sw";
+				#mbox-cells = <1>;
+				reg = <0>;
+				interrupts = <9 1>, <10 1>, <11 1>, <12 1>,
+					     <13 1>, <14 1>, <15 1>, <16 1>,
+					     <17 1>, <18 1>, <19 1>, <20 1>,
+					     <21 1>, <22 1>, <23 1>, <24 1>,
+					     <25 1>, <26 1>, <27 1>, <28 1>,
+					     <29 1>, <30 1>, <31 1>;
+				interrupt-names = "mbox_9", "mbox_10", "mbox_11", "mbox_12",
+						  "mbox_13", "mbox_14", "mbox_15", "mbox_16",
+						  "mbox_17", "mbox_18", "mbox_19", "mbox_20",
+						  "mbox_21", "mbox_22", "mbox_23", "mbox_24",
+						  "mbox_25", "mbox_26", "mbox_27", "mbox_28",
+						  "mbox_29", "mbox_30", "mbox_31";
+				interrupt-parent = <&plic_sw>;
+				status = "disabled";
+			};
 		};
 
 		mtimer: timer@e6000000 {