From 6caf803a41ec7844ccf4815014ed1e9cc17e371e Mon Sep 17 00:00:00 2001 From: Jimmy Zheng Date: Mon, 30 Sep 2024 16:00:01 +0800 Subject: [PATCH] dts: bindings: mbox: rename plic-sw to mbox-plic-sw Renamed andestech,plic-sw to andestech,mbox-plic-sw because the mbox node is based on the PLIC interrupt controller node instead using the plic hardware directly. Signed-off-by: Jimmy Zheng --- .../adp_xc7k_ae350/adp_xc7k_ae350.dts | 4 ++++ ...ic-sw.yaml => andestech,mbox-plic-sw.yaml} | 11 +++-------- dts/riscv/andes/andes_v5_ae350.dtsi | 19 +++++++++++++++++++ 3 files changed, 26 insertions(+), 8 deletions(-) rename dts/bindings/mbox/{andestech,plic-sw.yaml => andestech,mbox-plic-sw.yaml} (54%) diff --git a/boards/andestech/adp_xc7k_ae350/adp_xc7k_ae350.dts b/boards/andestech/adp_xc7k_ae350/adp_xc7k_ae350.dts index 58c91613057..09763df9fff 100644 --- a/boards/andestech/adp_xc7k_ae350/adp_xc7k_ae350.dts +++ b/boards/andestech/adp_xc7k_ae350/adp_xc7k_ae350.dts @@ -215,3 +215,7 @@ &dma0 { status = "okay"; }; + +&mbox { + status = "okay"; +}; diff --git a/dts/bindings/mbox/andestech,plic-sw.yaml b/dts/bindings/mbox/andestech,mbox-plic-sw.yaml similarity index 54% rename from dts/bindings/mbox/andestech,plic-sw.yaml rename to dts/bindings/mbox/andestech,mbox-plic-sw.yaml index f054d8c206b..3aa45bfd3b6 100644 --- a/dts/bindings/mbox/andestech,plic-sw.yaml +++ b/dts/bindings/mbox/andestech,mbox-plic-sw.yaml @@ -5,20 +5,15 @@ # description: | - This is a representation of AndesTech PLIC-SW node + This is a representation of AndesTech MBOX PLIC-SW node -compatible: "andestech,plic-sw" +compatible: "andestech,mbox-plic-sw" include: [base.yaml, mailbox-controller.yaml] properties: - reg: + interrupts: required: true - channel-max: - type: int - required: true - description: Supported channels max - mbox-cells: - channel diff --git a/dts/riscv/andes/andes_v5_ae350.dtsi b/dts/riscv/andes/andes_v5_ae350.dtsi index 1090dc5417e..a4edbb613c0 100644 --- a/dts/riscv/andes/andes_v5_ae350.dtsi +++ b/dts/riscv/andes/andes_v5_ae350.dtsi @@ -193,6 +193,25 @@ &cpu6_intc 3 &cpu7_intc 3>; #size-cells = <0>; + mbox: mbox-controller@0 { + compatible = "andestech,mbox-plic-sw"; + #mbox-cells = <1>; + reg = <0>; + interrupts = <9 1>, <10 1>, <11 1>, <12 1>, + <13 1>, <14 1>, <15 1>, <16 1>, + <17 1>, <18 1>, <19 1>, <20 1>, + <21 1>, <22 1>, <23 1>, <24 1>, + <25 1>, <26 1>, <27 1>, <28 1>, + <29 1>, <30 1>, <31 1>; + interrupt-names = "mbox_9", "mbox_10", "mbox_11", "mbox_12", + "mbox_13", "mbox_14", "mbox_15", "mbox_16", + "mbox_17", "mbox_18", "mbox_19", "mbox_20", + "mbox_21", "mbox_22", "mbox_23", "mbox_24", + "mbox_25", "mbox_26", "mbox_27", "mbox_28", + "mbox_29", "mbox_30", "mbox_31"; + interrupt-parent = <&plic_sw>; + status = "disabled"; + }; }; mtimer: timer@e6000000 {