2019-04-06 21:08:09 +08:00
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/* SPDX-License-Identifier: Apache-2.0 */
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2018-05-15 20:18:57 +08:00
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/dts-v1/;
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2018-10-14 22:37:38 +08:00
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#include <riscv32-fe310.dtsi>
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2018-05-15 20:18:57 +08:00
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/ {
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2018-10-14 22:37:38 +08:00
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model = "SiFive HiFive 1";
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compatible = "sifive,hifive1";
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2018-05-15 20:18:57 +08:00
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chosen {
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zephyr,console = &uart0;
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2018-11-27 19:11:04 +08:00
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zephyr,shell-uart = &uart0;
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2019-05-01 03:33:18 +08:00
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zephyr,sram = &dtim;
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2019-05-01 03:33:43 +08:00
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zephyr,flash = &flash0;
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2018-05-15 20:18:57 +08:00
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};
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2018-10-14 22:37:38 +08:00
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};
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&gpio0 {
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2019-06-15 01:31:16 +08:00
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status = "okay";
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2018-05-15 20:18:57 +08:00
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};
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&uart0 {
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2019-06-15 01:31:16 +08:00
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status = "okay";
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2018-05-15 20:18:57 +08:00
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current-speed = <115200>;
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2018-10-14 22:37:38 +08:00
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clock-frequency = <16000000>;
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2018-05-15 20:18:57 +08:00
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};
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2018-10-14 22:37:38 +08:00
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&uart1 {
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clock-frequency = <16000000>;
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};
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&spi0 {
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2019-06-15 01:31:16 +08:00
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status = "okay";
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2019-05-01 03:33:43 +08:00
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x10014000 0x1000 0x20400000 0xc00000>;
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flash0: flash@0 {
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compatible = "issi,is25lp128", "jedec,spi-nor";
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2019-10-27 22:06:40 +08:00
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size = <134217728>;
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2019-07-19 23:19:02 +08:00
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label = "FLASH0";
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2019-07-22 18:42:00 +08:00
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jedec-id = [96 60 18];
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2019-05-01 03:33:43 +08:00
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reg = <0>;
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2019-07-17 02:09:19 +08:00
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// Dummy entry
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spi-max-frequency = <0>;
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2019-05-01 03:33:43 +08:00
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};
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2018-10-14 22:37:38 +08:00
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};
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