20 lines
789 B
Plaintext
20 lines
789 B
Plaintext
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These files are a Nios II/F CPU design provided by Altera for evaluating
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Zephyr on Nios II. This design is intended for the Altera MAX10 10M50 Rec C
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development board. You can find more information about this board here:
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https://www.altera.com/products/boards_and_kits/dev-kits/altera/max-10-fpga-development-kit.html
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You will need the Quartus SDK in order to modify this CPU or flash it onto
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a supported device. The Lite version of Quartus may be obtained without charge
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from the following link:
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http://dl.altera.com/?edition=lite
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To flash this CPU, use the nios2-configure-sof tool:
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$ nios2-configure-sof ghrd_10m50da.sof
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The 'make flash' target will also package up the kernel and CPU into a single
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.pof file which will then put the image onto the device using quartus_pgm tool.
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