zephyr/soc/riscv/riscv-privilege/virt/soc.h

/*
 * Copyright (c) 2020 Cobham Gaisler AB
 *
 * SPDX-License-Identifier: Apache-2.0
 */

#ifndef __RISCV_VIRT_SOC_H_
#define __RISCV_VIRT_SOC_H_

#include <soc_common.h>
#include <devicetree.h>

#define SIFIVE_SYSCON_TEST           0x00100000
#define RISCV_MTIME_BASE             0x0200BFF8
#define RISCV_MTIMECMP_BASE          0x02004000

#endif
soc/riscv: add the QEMU "RISC-V VirtIO board" The QEMU RISC-V VirtIO board is capable: - 8 x CPU - 256 MiB RAM - PMP - PCI - ISA string: RVnnIMAFDCSU - mul/div - FPU with double precision - MMU - Compressed instructions Devicetree was extracted from QEMU as described in virt.dtsi. The same .dtsi SOC description is used for 32-bit and 64-bit. Signed-off-by: Martin Åberg <martin.aberg@gaisler.com> 2020-12-09 01:54:43 +08:00			`/*`
			`* Copyright (c) 2020 Cobham Gaisler AB`
			`*`
			`* SPDX-License-Identifier: Apache-2.0`
			`*/`

			`#ifndef __RISCV_VIRT_SOC_H_`
			`#define __RISCV_VIRT_SOC_H_`

			`#include <soc_common.h>`
			`#include <devicetree.h>`

soc/riscv: support reboot for QEMU RISC-V VirtIO This patch adds reboot function for QEMU RISC-V VirtIO board. Signed-off-by: Katsuhiro Suzuki <katsuhiro@katsuster.net> 2021-02-03 19:09:17 +08:00			`#define SIFIVE_SYSCON_TEST 0x00100000`
soc/riscv: add the QEMU "RISC-V VirtIO board" The QEMU RISC-V VirtIO board is capable: - 8 x CPU - 256 MiB RAM - PMP - PCI - ISA string: RVnnIMAFDCSU - mul/div - FPU with double precision - MMU - Compressed instructions Devicetree was extracted from QEMU as described in virt.dtsi. The same .dtsi SOC description is used for 32-bit and 64-bit. Signed-off-by: Martin Åberg <martin.aberg@gaisler.com> 2020-12-09 01:54:43 +08:00			`#define RISCV_MTIME_BASE 0x0200BFF8`
			`#define RISCV_MTIMECMP_BASE 0x02004000`

			`#endif`