77 lines
1.7 KiB
C
77 lines
1.7 KiB
C
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/* Copyright (c) 2023 Intel Corporation
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef __ZEPHYR_CAVS_LIB_ASM_MEMORY_MANAGEMENT_H__
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#define __ZEPHYR_CAVS_LIB_ASM_MEMORY_MANAGEMENT_H__
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#ifdef _ASMLANGUAGE
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#define HSPGCTL0 0x71D10
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#define HSRMCTL0 0x71D14
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#define HSPGISTS0 0x71D18
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#define LSPGCTL 0x71D50
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#define LSRMCTL 0x71D54
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#define LSPGISTS 0x71D58
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#define SHIM_HSPGCTL(x) (HSPGCTL0 + 0x10 * (x))
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#define SHIM_HSPGISTS(x) (HSPGISTS0 + 0x10 * (x))
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#define LPSRAM_MASK 0x1
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/**
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* Macro powers down entire HPSRAM. On entry literals and code for section from
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* where this code is executed need to be placed in memory which is not
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* HPSRAM (in case when this code is located in HPSRAM, lock memory in L1$ or
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* L1 SRAM)
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*/
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.macro m_cavs_hpsram_power_down_entire ax, ay, az
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/* SEGMENT #0 */
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movi \az, SHIM_HSPGCTL(0)
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movi \ax, SHIM_HSPGISTS(0)
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movi \ay, 0x1FFFFFFF /* HPSRAM_MASK(0) */
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s32i \ay, \ax, 0
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memw
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1 :
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l32i \ax, \az, 0
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bne \ax, \ay, 1b
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/* SEGMENT #1 */
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movi \az, SHIM_HSPGCTL(1)
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movi \ax, SHIM_HSPGISTS(1)
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movi \ay, 0x0FFFFFFF /* HPSRAM_MASK(1) */
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s32i \ay, \ax, 0
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memw
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1 :
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l32i \ax, \az, 0
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bne \ax, \ay, 1b
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.endm
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.macro m_cavs_hpsram_power_change segment_index, mask, ax, ay, az
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movi \ax, SHIM_HSPGCTL(\segment_index)
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movi \ay, SHIM_HSPGISTS(\segment_index)
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s32i \mask, \ax, 0
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memw
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/* assumed that HDA shared dma buffer will be in LPSRAM */
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1 :
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l32i \ax, \ay, 0
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bne \ax, \mask, 1b
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.endm
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.macro m_cavs_lpsram_power_down_entire ax, ay, az, loop_cnt_addr
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movi \az, LSPGISTS
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movi \ax, LSPGCTL
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movi \ay, LPSRAM_MASK
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s32i \ay, \ax, 0
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memw
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/* assumed that HDA shared dma buffer will be in LPSRAM */
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movi \ax, \loop_cnt_addr
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l32i \ax, \ax, 0
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1 :
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addi \ax, \ax, -1
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bnez \ax, 1b
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.endm
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#endif
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#endif
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