64 lines
1.4 KiB
Plaintext
64 lines
1.4 KiB
Plaintext
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/*
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* Copyright (c) 2024 Antmicro <www.antmicro.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/dt-bindings/interrupt-controller/arm-gic.h>
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-r8f";
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reg = <0>;
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};
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};
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soc {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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ranges;
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interrupt-parent = < &gic >;
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flash0: flash@c0000000 {
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compatible = "soc-nv-flash";
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reg = < 0xc0000000 0x2000000 >;
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};
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sram0: memory@0 {
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compatible = "mmio-sram";
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reg = < 0x0 0x4000000 >;
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};
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uart0: uart@ff000000 {
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compatible = "xlnx,xuartps";
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reg = < 0xff000000 0x4c >;
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status = "disabled";
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interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL
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IRQ_DEFAULT_PRIORITY>;
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interrupt-names = "irq_0";
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};
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ttc0: timer@ff110000 {
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compatible = "xlnx,ttcps";
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status = "okay";
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interrupts = < 0x0 0x24 0x2 0xa0 >,
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< 0x0 0x25 0x2 0xa0 >,
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< 0x0 0x26 0x2 0xa0 >;
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interrupt-names = "irq_0", "irq_1", "irq_2";
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reg = < 0xff110000 0x1000 >;
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clock-frequency = < 5000000 >;
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};
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gic: interrupt-controller@f9000000 {
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compatible = "arm,gic-v1", "arm,gic";
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reg = < 0xf9000000 0x1000 >, < 0xf9001000 0x100 >;
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interrupt-controller;
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#interrupt-cells = < 0x4 >;
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status = "okay";
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phandle = < 0x1 >;
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};
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};
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};
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