/*
 * Copyright (c) 2024 Antmicro <www.antmicro.com>
 *
 * SPDX-License-Identifier: Apache-2.0
 */

#include <zephyr/dt-bindings/interrupt-controller/arm-gic.h>

/ {
	#address-cells = <1>;
	#size-cells = <1>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;
		cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-r8f";
			reg = <0>;
		};
	};
	soc {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "simple-bus";
		ranges;
		interrupt-parent = < &gic >;
		flash0: flash@c0000000 {
			compatible = "soc-nv-flash";
			reg = < 0xc0000000 0x2000000 >;
		};
		sram0: memory@0 {
			compatible = "mmio-sram";
			reg = < 0x0 0x4000000 >;
		};
		uart0: uart@ff000000 {
			compatible = "xlnx,xuartps";
			reg = < 0xff000000 0x4c >;
			status = "disabled";
			interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL
					IRQ_DEFAULT_PRIORITY>;
			interrupt-names = "irq_0";
		};
		ttc0: timer@ff110000 {
			compatible = "xlnx,ttcps";
			status = "okay";
			interrupts = < 0x0 0x24 0x2 0xa0 >,
				< 0x0 0x25 0x2 0xa0 >,
				< 0x0 0x26 0x2 0xa0 >;
			interrupt-names = "irq_0", "irq_1", "irq_2";
			reg = < 0xff110000 0x1000 >;
			clock-frequency = < 5000000 >;
		};
		gic: interrupt-controller@f9000000 {
			compatible = "arm,gic-v1", "arm,gic";
			reg = < 0xf9000000 0x1000 >, < 0xf9001000 0x100 >;
			interrupt-controller;
			#interrupt-cells = < 0x4 >;
			status = "okay";
			phandle = < 0x1 >;
		};
	};
};