2018-08-16 06:41:21 +08:00
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if SOC_SERIES_RISCV32_SIFIVE_FREEDOM
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2017-03-15 05:15:59 +08:00
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config SOC_SERIES
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string
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2018-08-16 06:41:21 +08:00
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default "sifive-freedom"
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2017-03-15 05:15:59 +08:00
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config SYS_CLOCK_HW_CYCLES_PER_SEC
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int
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default 32768
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config RISCV_SOC_INTERRUPT_INIT
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bool
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default y
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config RISCV_HAS_CPU_IDLE
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bool
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default y
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config RISCV_HAS_PLIC
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bool
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default y
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config NUM_IRQS
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int
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default 64
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config XIP
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bool
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default y
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config RISCV_ROM_BASE_ADDR
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hex
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default 0x20400000
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config RISCV_ROM_SIZE
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hex
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default 0xC00000
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config RISCV_RAM_BASE_ADDR
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hex
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default 0x80000000
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config RISCV_RAM_SIZE
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hex
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default 0x4000
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2018-08-16 06:41:21 +08:00
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endif # SOC_SERIES_RISCV32_SIFIVE_FREEDOM
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