2015-05-21 00:40:39 +08:00
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# Kconfig - x86 general configuration options
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#
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# Copyright (c) 2014-2015 Wind River Systems, Inc.
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#
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2015-10-07 00:00:37 +08:00
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# Licensed under the Apache License, Version 2.0 (the "License");
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# you may not use this file except in compliance with the License.
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# You may obtain a copy of the License at
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2015-05-21 00:40:39 +08:00
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#
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2015-10-07 00:00:37 +08:00
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# http://www.apache.org/licenses/LICENSE-2.0
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2015-05-21 00:40:39 +08:00
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#
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2015-10-07 00:00:37 +08:00
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# Unless required by applicable law or agreed to in writing, software
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# distributed under the License is distributed on an "AS IS" BASIS,
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# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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# See the License for the specific language governing permissions and
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# limitations under the License.
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2015-05-21 00:40:39 +08:00
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#
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2016-03-16 01:24:36 +08:00
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choice
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prompt "x86 SoC Selection"
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depends on X86
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source "arch/x86/soc/*/Kconfig.soc"
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endchoice
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menu "x86 Options"
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2015-10-09 18:20:52 +08:00
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depends on X86
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2015-05-26 22:31:43 +08:00
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2015-10-09 18:20:52 +08:00
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config ARCH
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2016-05-25 07:17:13 +08:00
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default "x86"
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2015-05-26 22:31:43 +08:00
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2015-12-15 01:56:38 +08:00
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2015-11-03 09:42:35 +08:00
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config ARCH_DEFCONFIG
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string
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default "arch/x86/defconfig"
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2015-06-10 22:25:07 +08:00
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2015-11-30 09:20:42 +08:00
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source "arch/x86/core/Kconfig"
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2015-10-15 03:46:41 +08:00
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2016-03-16 00:02:42 +08:00
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#
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# Hidden CPU family configs which are to be selected by
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# individual SoC.
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#
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2015-06-12 05:05:13 +08:00
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config CPU_ATOM
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2016-03-16 00:02:42 +08:00
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# Hidden
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bool
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2015-07-23 01:34:59 +08:00
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select CMOV
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2016-03-16 00:24:49 +08:00
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select CPU_HAS_FPU
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2015-06-12 05:05:13 +08:00
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help
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This option signifies the use of a CPU from the Atom family.
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2015-06-10 22:25:07 +08:00
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config CPU_MINUTEIA
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2016-03-16 00:02:42 +08:00
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# Hidden
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bool
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2015-06-10 22:25:07 +08:00
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help
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This option signifies the use of a CPU from the Minute IA family.
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2016-03-16 00:02:42 +08:00
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#
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# End hidden CPU family configs
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#
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2015-06-10 22:25:07 +08:00
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2016-03-16 00:24:49 +08:00
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config CPU_HAS_FPU
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# Hidden config selected by CPU family
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bool
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default n
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help
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This option is enabled when the CPU has hardware floating point
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unit.
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2015-11-30 09:20:42 +08:00
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menu "Processor Capabilities"
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2016-03-14 20:23:09 +08:00
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config X86_IAMCU
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bool
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default n
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prompt "IAMCU calling convention"
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help
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The IAMCU calling convention changes the X86 C calling convention to
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pass some arguments via registers allowing for code size and performance
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improvements. Great care needs to be taken if you have assembly code
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that will be called from C or C code called from assembly code, the
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assembly code will need to be updated to conform to the new calling
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convention. If in doubt say N
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2015-11-30 09:20:42 +08:00
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menu "Floating Point Options"
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2016-03-16 00:24:49 +08:00
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depends on CPU_HAS_FPU
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2015-08-04 22:05:24 +08:00
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2016-05-25 07:17:13 +08:00
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config FLOAT
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2015-11-30 09:20:42 +08:00
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bool
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prompt "Floating point registers"
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default n
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2015-08-04 22:05:24 +08:00
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help
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2015-11-30 09:20:42 +08:00
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This option allows tasks and fibers to use the floating point registers.
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By default, only a single task or fiber may use the registers, and only
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the x87 FPU/MMX registers may be used.
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2015-08-04 22:05:24 +08:00
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2015-11-30 09:20:42 +08:00
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Disabling this option means that any task or fiber that uses a
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floating point register will get a fatal exception.
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x86: remove dynamically generated IRQ and exception code
We are interested in supporting some XIP x86 platforms which are
unable to fetch CPU instructions from system RAM. This requires
refactoring our dynamic IRQ/exc code which currently synthesizes
assembly language instructions to create IRQ stubs on-the-fly.
Instead, a new approach is taken. Given that the configuration at
build time specifies the number of required stubs, use this
to generate a build time a set of tiny stub functions which simply
push a 'stub id' and then call common dynamic interrupt code.
The handler function and handler argument is saved in a table keyed by
this stub id.
CONFIG_EOI_HANDLER_SUPPORTED removed, the code hasn't been conditionally
compiled for some time and in all cases we call _loapic_eoi() when
finished with an interrupt.
Some other out-of-date verbiage in comments related to supporting
non-APIC removed.
Previously, when dynamic exceptions were created a pointer would
be passed in by the caller reserving ram for the stub code. Since
this is no longer feasible, two new Kconfig options have been added.
CONFIG_NUM_DYNAMIC_EXC_STUBS and CONFIG_NUM_DYNAMIC_EXC_NO_ERR_STUBS
control how many stubs are created for exceptions that push
an error code, and no error code, respectively.
SW Interrupts are no longer triggered by "int <vector>" hard-coded
assembly instructions. Instead this is done by sending a self-directed
inter-processor interrupt from the LOAPIC, using a new API
loapic_int_vect_trigger(). In this way we get rid of dynamically
generated code in irq_test_common.h.
All interrupts call _loapic_eoi() when finished, since this is now
the right thing to do for all IRQs, including SW interrupts.
_irq_handler_set() for x86 no longer requires the old function pointer
to be supplied.
Change-Id: I78993d3d00dd153c9051c518b417cce8d3acee9e
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2015-10-20 05:10:53 +08:00
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2016-05-25 07:17:13 +08:00
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config FP_SHARING
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2015-11-30 09:20:42 +08:00
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bool
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prompt "Floating point register sharing"
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depends on FLOAT
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default n
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x86: remove dynamically generated IRQ and exception code
We are interested in supporting some XIP x86 platforms which are
unable to fetch CPU instructions from system RAM. This requires
refactoring our dynamic IRQ/exc code which currently synthesizes
assembly language instructions to create IRQ stubs on-the-fly.
Instead, a new approach is taken. Given that the configuration at
build time specifies the number of required stubs, use this
to generate a build time a set of tiny stub functions which simply
push a 'stub id' and then call common dynamic interrupt code.
The handler function and handler argument is saved in a table keyed by
this stub id.
CONFIG_EOI_HANDLER_SUPPORTED removed, the code hasn't been conditionally
compiled for some time and in all cases we call _loapic_eoi() when
finished with an interrupt.
Some other out-of-date verbiage in comments related to supporting
non-APIC removed.
Previously, when dynamic exceptions were created a pointer would
be passed in by the caller reserving ram for the stub code. Since
this is no longer feasible, two new Kconfig options have been added.
CONFIG_NUM_DYNAMIC_EXC_STUBS and CONFIG_NUM_DYNAMIC_EXC_NO_ERR_STUBS
control how many stubs are created for exceptions that push
an error code, and no error code, respectively.
SW Interrupts are no longer triggered by "int <vector>" hard-coded
assembly instructions. Instead this is done by sending a self-directed
inter-processor interrupt from the LOAPIC, using a new API
loapic_int_vect_trigger(). In this way we get rid of dynamically
generated code in irq_test_common.h.
All interrupts call _loapic_eoi() when finished, since this is now
the right thing to do for all IRQs, including SW interrupts.
_irq_handler_set() for x86 no longer requires the old function pointer
to be supplied.
Change-Id: I78993d3d00dd153c9051c518b417cce8d3acee9e
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2015-10-20 05:10:53 +08:00
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help
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2015-11-30 09:20:42 +08:00
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This option allows multiple tasks and fibers to use the floating point
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registers. Any task that uses the floating point registers must provide
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stack space where the kernel can save these registers during context
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switches; a task that uses only the x87 FPU/MMX registers must provide
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108 bytes of added stack space, while a task the uses the SSE registers
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must provide 464 bytes of added stack space.
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x86: remove dynamically generated IRQ and exception code
We are interested in supporting some XIP x86 platforms which are
unable to fetch CPU instructions from system RAM. This requires
refactoring our dynamic IRQ/exc code which currently synthesizes
assembly language instructions to create IRQ stubs on-the-fly.
Instead, a new approach is taken. Given that the configuration at
build time specifies the number of required stubs, use this
to generate a build time a set of tiny stub functions which simply
push a 'stub id' and then call common dynamic interrupt code.
The handler function and handler argument is saved in a table keyed by
this stub id.
CONFIG_EOI_HANDLER_SUPPORTED removed, the code hasn't been conditionally
compiled for some time and in all cases we call _loapic_eoi() when
finished with an interrupt.
Some other out-of-date verbiage in comments related to supporting
non-APIC removed.
Previously, when dynamic exceptions were created a pointer would
be passed in by the caller reserving ram for the stub code. Since
this is no longer feasible, two new Kconfig options have been added.
CONFIG_NUM_DYNAMIC_EXC_STUBS and CONFIG_NUM_DYNAMIC_EXC_NO_ERR_STUBS
control how many stubs are created for exceptions that push
an error code, and no error code, respectively.
SW Interrupts are no longer triggered by "int <vector>" hard-coded
assembly instructions. Instead this is done by sending a self-directed
inter-processor interrupt from the LOAPIC, using a new API
loapic_int_vect_trigger(). In this way we get rid of dynamically
generated code in irq_test_common.h.
All interrupts call _loapic_eoi() when finished, since this is now
the right thing to do for all IRQs, including SW interrupts.
_irq_handler_set() for x86 no longer requires the old function pointer
to be supplied.
Change-Id: I78993d3d00dd153c9051c518b417cce8d3acee9e
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2015-10-20 05:10:53 +08:00
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2016-05-25 07:17:13 +08:00
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config SSE
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2015-11-30 09:20:42 +08:00
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bool
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prompt "SSE registers"
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depends on FLOAT
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2015-08-04 22:05:24 +08:00
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default n
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help
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2015-11-30 09:20:42 +08:00
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This option enables the use of SSE registers by tasks and fibers.
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2015-08-04 22:05:24 +08:00
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2015-11-30 09:20:42 +08:00
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config SSE_FP_MATH
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bool
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prompt "Compiler-generated SSEx instructions"
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depends on SSE
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2015-11-18 06:08:45 +08:00
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default n
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help
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2015-11-30 09:20:42 +08:00
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This option allows the compiler to generate SSEx instructions for
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performing floating point math. This can greatly improve performance
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when exactly the same operations are to be performed on multiple
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data objects; however, it can also significantly reduce performance
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when pre-emptive task switches occur because of the larger register
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set that must be saved and restored.
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2015-07-30 01:59:01 +08:00
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2015-11-30 09:20:42 +08:00
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Disabling this option means that the compiler utilizes only the
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x87 instruction set for floating point operations.
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2016-03-14 20:23:09 +08:00
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endmenu
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2015-06-10 22:25:07 +08:00
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2016-01-19 06:36:00 +08:00
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choice
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prompt "Reboot implementation"
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depends on REBOOT
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default REBOOT_RST_CNT
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config REBOOT_RST_CNT
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bool
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prompt "Reboot via RST_CNT register"
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help
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Reboot via the RST_CNT register, going back to BIOS.
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endchoice
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2015-06-10 22:25:07 +08:00
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config ISA_IA32
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bool
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2015-07-30 02:37:10 +08:00
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default y
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2015-06-10 22:25:07 +08:00
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help
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This option signifies the use of a CPU based on the Intel IA-32
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instruction set architecture.
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2015-09-23 20:00:05 +08:00
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config IA32_LEGACY_IO_PORTS
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bool
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prompt "Support IA32 legacy IO ports"
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default n
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depends on ISA_IA32
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help
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This option enables IA32 legacy IO ports. Note these are much slower
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than memory access, so they should be used in last resort.
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2015-07-23 01:34:59 +08:00
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config CMOV
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def_bool n
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2015-06-10 22:25:07 +08:00
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help
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2015-07-23 01:34:59 +08:00
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This option signifies the use of an Intel CPU that supports
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the CMOV instruction.
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2015-06-10 22:25:07 +08:00
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2015-09-19 04:36:57 +08:00
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config CACHE_LINE_SIZE_DETECT
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bool
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prompt "Detect cache line size at runtime"
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default y
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help
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This option enables querying the CPUID register for finding the cache line
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size at the expense of taking more memory and code and a slightly increased
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boot time.
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If the CPU's cache line size is known in advance, disable this option and
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manually enter the value for CACHE_LINE_SIZE.
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2015-06-10 22:25:07 +08:00
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config CACHE_LINE_SIZE
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2015-09-19 04:36:57 +08:00
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int
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prompt "Cache line size" if !CACHE_LINE_SIZE_DETECT
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default 0 if CACHE_LINE_SIZE_DETECT
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2015-07-11 02:17:56 +08:00
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default 64 if CPU_ATOM
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2015-06-10 22:25:07 +08:00
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default 0
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help
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Size in bytes of a CPU cache line.
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2015-09-19 04:36:57 +08:00
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Detect automatically at runtime by selecting CACHE_LINE_SIZE_DETECT.
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config CLFLUSH_INSTRUCTION_SUPPORTED
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bool
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2016-03-01 00:12:40 +08:00
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prompt "CLFLUSH instruction supported"
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depends on !CLFLUSH_DETECT && CACHE_FLUSHING
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2015-09-19 04:36:57 +08:00
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default n
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help
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An implementation of sys_cache_flush() that uses CLFLUSH is made
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available, instead of the one using WBINVD.
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This option should only be enabled if it is known in advance that the
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CPU supports the CLFLUSH instruction. It disables runtime detection of
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CLFLUSH support thereby reducing both memory footprint and boot time.
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config CLFLUSH_DETECT
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bool
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prompt "Detect support of CLFLUSH instruction at runtime"
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2016-03-01 00:12:40 +08:00
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depends on CACHE_FLUSHING
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default n
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2015-09-19 04:36:57 +08:00
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help
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This option should be enabled if it is not known in advance whether the
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CPU supports the CLFLUSH instruction or not.
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The CPU is queried at boot time to determine which of the multiple
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implementations of sys_cache_flush() linked into the image is the
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correct one to use.
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If the CPU's support (or lack thereof) of CLFLUSH is known in advance, then
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disable this option and set CLFLUSH_INSTRUCTION_SUPPORTED as appropriate.
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config ARCH_CACHE_FLUSH_DETECT
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bool
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default y
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depends on CLFLUSH_DETECT
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2015-11-30 09:20:42 +08:00
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config CACHE_FLUSHING
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bool
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default n
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prompt "Enable cache flushing mechanism"
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help
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This links in the sys_cache_flush() function. A mechanism for flushing the
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cache must be selected as well. By default, that mechanism is discovered at
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runtime.
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2015-06-10 22:25:07 +08:00
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endmenu
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2016-08-18 07:33:08 +08:00
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menu "Board Capabilities"
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2015-11-30 09:20:42 +08:00
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config PIC_DISABLE
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bool "Disable PIC"
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2015-09-29 22:08:58 +08:00
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default n
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2015-08-01 04:52:22 +08:00
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help
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2015-11-30 09:20:42 +08:00
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This option disables all interrupts on the PIC
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2015-08-01 04:52:22 +08:00
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2015-11-30 09:20:42 +08:00
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config IRQ_OFFLOAD
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bool "Enable IRQ offload"
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default n
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help
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Enable irq_offload() API which allows functions to be synchronously
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run in interrupt context. Uses one entry in the IDT. Mainly useful
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for test cases.
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2015-08-01 04:52:22 +08:00
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2015-12-10 02:18:30 +08:00
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config IRQ_OFFLOAD_VECTOR
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int "IDT vector to use for IRQ offload"
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default 63 if MVIC
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2016-03-26 05:30:50 +08:00
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default 32 if !MVIC
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2015-12-10 02:18:30 +08:00
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range 32 255
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depends on IRQ_OFFLOAD
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help
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Specify the IDT vector to use for the IRQ offload interrupt handler.
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The default should be fine for most arches, but on systems like MVIC
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where there is a fixed IRQ-to-vector mapping another value may be
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needed to avoid collision.
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2015-03-13 06:15:28 +08:00
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config XIP
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default n
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2016-08-03 03:05:08 +08:00
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config X86_FIXED_IRQ_MAPPING
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bool
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default n
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help
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Specify whether the current interrupt controller in use has a fixed
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mapping between IDT vectors and IRQ lines.
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2015-03-13 06:15:28 +08:00
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endmenu
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2015-06-20 22:38:01 +08:00
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2015-07-30 01:59:01 +08:00
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2015-12-17 21:54:35 +08:00
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source "arch/x86/soc/*/Kconfig"
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2015-11-22 20:24:14 +08:00
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2015-10-09 18:20:52 +08:00
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endmenu
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