OrgZephyr/zephyr
OrgZephyr
/
zephyr
mirror of https://github.com/zephyrproject-rtos/zephyr.git
1
0
Fork 0
Code Issues Releases Wiki Activity
zephyr/arch/nios2/soc/nios2f-zephyr/Kconfig.defconfig

45 lines
642 B
Plaintext
Raw Normal View History

nios2f-zephyr: add Nios II/f core This core has extra debugging features useful for this bring-up exercise. Change-Id: I619bc8768acb1d9be8699a6e238168f47e605f3d Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-06-16 02:51:03 +08:00
if SOC_NIOS2F_ZEPHYR
config SOC
string
default nios2f-zephyr
config SYS_CLOCK_HW_CYCLES_PER_SEC
int
nios2: properly set SYS_CLOCK_HW_CYCLES_PER_SEC This is a workaround until we can modify the kernel to pull this value out of system.h instead of Kconfig. Change-Id: Iaafa9003d2bbcb5b38a050c371466a206f716ae7 Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-06-22 04:59:36 +08:00
default 50000000
nios2f-zephyr: add Nios II/f core This core has extra debugging features useful for this bring-up exercise. Change-Id: I619bc8768acb1d9be8699a6e238168f47e605f3d Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-06-16 02:51:03 +08:00
arch: nios2: enable System ID soft IP driver The system ID core is a simple read-only device that provides Qsys systems with a unique identifer. Nios-II processor systems use the system ID core to verify that an executable program was compiled targeting the actual hardware image configured in the target FPGA. Signed-off-by: Ramakrishna Pallala <ramakrishna.pallala@intel.com>
2017-12-13 09:08:33 +08:00
config ALTERA_AVALON_SYSID
def_bool y
drivers: gpio: add support for Altera Nios-II PIO controller The PIO cores on Altera Nios-II processors can be used for GPIOs and each PIO core can be configured as Input only, Output only or as Bidirectional port from the Qsys tool. The present Nios-II softcpu image on the Zephyr only has the support for Output only port and the PIOs[0:3] are wired to LED[0:3] on the Altera MAX10 board. Signed-off-by: Ramakrishna Pallala <ramakrishna.pallala@intel.com>
2017-12-16 17:25:09 +08:00
if GPIO_ALTERA_NIOS2
config ALTERA_AVALON_PIO
def_bool y
endif # GPIO_ALTERA_NIOS2
altera_max10: enable and use 16550 UART The 16550 will now be the default console device. Change-Id: I92a6b49984b055e7d5f5c97e5192150be0d5c5c7 Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-07-15 04:41:34 +08:00
if UART_NS16550
config UART_NS16550_PCI
def_bool n
config UART_NS16550_PORT_0
def_bool y
if UART_NS16550_PORT_0
config UART_NS16550_PORT_0_NAME
default "UART_0"
config UART_NS16550_PORT_0_IRQ_PRI
default 3
config UART_NS16550_PORT_0_BAUD_RATE
default 115200
config UART_NS16550_PORT_0_OPTIONS
default 0
endif # UART_NS16550_PORT_0
endif # UART_NS16550
endif # SOC_NIOS2F_ZEPHYR