The PIO cores on Altera Nios-II processors can be used
for GPIOs and each PIO core can be configured as Input only,
Output only or as Bidirectional port from the Qsys tool.
The present Nios-II softcpu image on the Zephyr only has the
support for Output only port and the PIOs[0:3] are wired to
LED[0:3] on the Altera MAX10 board.
Signed-off-by: Ramakrishna Pallala <ramakrishna.pallala@intel.com>
The system ID core is a simple read-only device that
provides Qsys systems with a unique identifer.
Nios-II processor systems use the system ID core to
verify that an executable program was compiled targeting
the actual hardware image configured in the target FPGA.
Signed-off-by: Ramakrishna Pallala <ramakrishna.pallala@intel.com>
The 16550 will now be the default console device.
Change-Id: I92a6b49984b055e7d5f5c97e5192150be0d5c5c7
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
This is a workaround until we can modify the kernel to pull this
value out of system.h instead of Kconfig.
Change-Id: Iaafa9003d2bbcb5b38a050c371466a206f716ae7
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
This core has extra debugging features useful for this bring-up
exercise.
Change-Id: I619bc8768acb1d9be8699a6e238168f47e605f3d
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Ramakrishna Pallala