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zephyr/arch/xtensa/core/swap.S

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Xtensa port: Added Xtensa specific code (C + S) files. Change-Id: I0dff0c33d8577cc70d4d5ee8f298db38c508ee73 Signed-off-by: Mazen NEIFER <mazen@nestwave.com>
2017-01-23 00:21:34 +08:00
/*
* Copyright (c) 2016 Cadence Design Systems, Inc.
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief kernel swapper code for Xtensa
*
kernel: tickless: Rename _Swap to allow creation of macro Future tickless kernel patches would be inserting some code before call to Swap. To enable this it will create a mcro named as the current _Swap which would call first the tickless kernel code and then call the real __swap() Jira: ZEP-339 Change-Id: Id778bfcee4f88982c958fcf22d7f04deb4bd572f Signed-off-by: Ramesh Thomas <ramesh.thomas@intel.com>
2017-04-07 06:30:27 +08:00
* This module implements the __swap() routine for the Xtensa architecture.
Xtensa port: Added Xtensa specific code (C + S) files. Change-Id: I0dff0c33d8577cc70d4d5ee8f298db38c508ee73 Signed-off-by: Mazen NEIFER <mazen@nestwave.com>
2017-01-23 00:21:34 +08:00
*/
#include <xtensa_context.h>
#include <kernel_arch_data.h>
#include <offsets_short.h>
.extern _kernel
kernel: tickless: Rename _Swap to allow creation of macro Future tickless kernel patches would be inserting some code before call to Swap. To enable this it will create a mcro named as the current _Swap which would call first the tickless kernel code and then call the real __swap() Jira: ZEP-339 Change-Id: Id778bfcee4f88982c958fcf22d7f04deb4bd572f Signed-off-by: Ramesh Thomas <ramesh.thomas@intel.com>
2017-04-07 06:30:27 +08:00
/* unsigned int __swap (unsigned int basepri); */
.globl __swap
.type __swap,@function
Xtensa port: Added Xtensa specific code (C + S) files. Change-Id: I0dff0c33d8577cc70d4d5ee8f298db38c508ee73 Signed-off-by: Mazen NEIFER <mazen@nestwave.com>
2017-01-23 00:21:34 +08:00
.align 4
kernel: tickless: Rename _Swap to allow creation of macro Future tickless kernel patches would be inserting some code before call to Swap. To enable this it will create a mcro named as the current _Swap which would call first the tickless kernel code and then call the real __swap() Jira: ZEP-339 Change-Id: Id778bfcee4f88982c958fcf22d7f04deb4bd572f Signed-off-by: Ramesh Thomas <ramesh.thomas@intel.com>
2017-04-07 06:30:27 +08:00
__swap:
Xtensa port: Added Xtensa specific code (C + S) files. Change-Id: I0dff0c33d8577cc70d4d5ee8f298db38c508ee73 Signed-off-by: Mazen NEIFER <mazen@nestwave.com>
2017-01-23 00:21:34 +08:00
#ifdef __XTENSA_CALL0_ABI__
addi sp, sp, -XT_SOL_FRMSZ
#else
entry sp, XT_SOL_FRMSZ
#endif
s32i a0, sp, XT_SOL_pc
s32i a2, sp, XT_SOL_ps
#ifdef __XTENSA_CALL0_ABI__
xtensa: fix numerous checkpatch issues Change-Id: I903f5f0692849fb9e7bf5d978b63b12bf1bd6e33 Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-02-11 04:58:08 +08:00
s32i a12, sp, XT_SOL_a12 /* save callee-saved registers */
Xtensa port: Added Xtensa specific code (C + S) files. Change-Id: I0dff0c33d8577cc70d4d5ee8f298db38c508ee73 Signed-off-by: Mazen NEIFER <mazen@nestwave.com>
2017-01-23 00:21:34 +08:00
s32i a13, sp, XT_SOL_a13
s32i a14, sp, XT_SOL_a14
s32i a15, sp, XT_SOL_a15
#else
xtensa: fix numerous checkpatch issues Change-Id: I903f5f0692849fb9e7bf5d978b63b12bf1bd6e33 Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-02-11 04:58:08 +08:00
/* Spill register windows. Calling xthal_window_spill() causes extra
* spills and reloads, so we will set things up to call the _nw version
* instead to save cycles.
*/
/* spills a4-a7 if needed */
movi a6, ~(PS_WOE_MASK|PS_INTLEVEL_MASK)
and a2, a2, a6 /* clear WOE, INTLEVEL */
addi a2, a2, XCHAL_EXCM_LEVEL /* set INTLEVEL */
Xtensa port: Added Xtensa specific code (C + S) files. Change-Id: I0dff0c33d8577cc70d4d5ee8f298db38c508ee73 Signed-off-by: Mazen NEIFER <mazen@nestwave.com>
2017-01-23 00:21:34 +08:00
wsr a2, PS
rsync
call0 xthal_window_spill_nw
xtensa: fix numerous checkpatch issues Change-Id: I903f5f0692849fb9e7bf5d978b63b12bf1bd6e33 Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-02-11 04:58:08 +08:00
l32i a2, sp, XT_SOL_ps /* restore PS */
Xtensa port: Added Xtensa specific code (C + S) files. Change-Id: I0dff0c33d8577cc70d4d5ee8f298db38c508ee73 Signed-off-by: Mazen NEIFER <mazen@nestwave.com>
2017-01-23 00:21:34 +08:00
addi a2, a2, XCHAL_EXCM_LEVEL
wsr a2, PS
#endif
#if XCHAL_CP_NUM > 0
xtensa: fix numerous checkpatch issues Change-Id: I903f5f0692849fb9e7bf5d978b63b12bf1bd6e33 Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-02-11 04:58:08 +08:00
/* Save coprocessor callee-saved state (if any). At this point CPENABLE
* should still reflect which CPs were in use (enabled).
*/
Xtensa port: Added Xtensa specific code (C + S) files. Change-Id: I0dff0c33d8577cc70d4d5ee8f298db38c508ee73 Signed-off-by: Mazen NEIFER <mazen@nestwave.com>
2017-01-23 00:21:34 +08:00
call0 _xt_coproc_savecs
#endif
movi a2, _kernel
movi a3, 0
l32i a4, a2, KERNEL_OFFSET(current) /* a4 := _kernel->current */
xtensa: fix numerous checkpatch issues Change-Id: I903f5f0692849fb9e7bf5d978b63b12bf1bd6e33 Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-02-11 04:58:08 +08:00
s32i a3, sp, XT_SOL_exit /* 0 to flag as solicited frame */
Xtensa port: Fixed assembly comments to be accurate with code. Change-Id: I7e0381cbefae916db515be4c10fe820dd4eddea6 Signed-off-by: Mazen NEIFER <mazen@nestwave.com>
2017-01-28 02:11:48 +08:00
s32i sp, a4, THREAD_OFFSET(sp) /* current->arch.topOfStack := sp */
Xtensa port: Set Swap function result to -EAGAIN. Change-Id: I70a651012d5da873c98f6b13ada5e80e67e18e0c Signed-off-by: Mazen NEIFER <mazen@nestwave.com>
2017-02-05 18:51:26 +08:00
/*
kernel: tickless: Rename _Swap to allow creation of macro Future tickless kernel patches would be inserting some code before call to Swap. To enable this it will create a mcro named as the current _Swap which would call first the tickless kernel code and then call the real __swap() Jira: ZEP-339 Change-Id: Id778bfcee4f88982c958fcf22d7f04deb4bd572f Signed-off-by: Ramesh Thomas <ramesh.thomas@intel.com>
2017-04-07 06:30:27 +08:00
* Set __swap()'s default return code to -EAGAIN. This eliminates the
Xtensa port: Set Swap function result to -EAGAIN. Change-Id: I70a651012d5da873c98f6b13ada5e80e67e18e0c Signed-off-by: Mazen NEIFER <mazen@nestwave.com>
2017-02-05 18:51:26 +08:00
* need for the timeout code to set it itself.
*/
movi a3, -11 /* a3 := -EAGAIN. TODO: Use a macro here insted of 11 */
s32i a3, a4, THREAD_OFFSET(retval) /* current->arch.retval := -EAGAIN */
Xtensa port: Added Xtensa specific code (C + S) files. Change-Id: I0dff0c33d8577cc70d4d5ee8f298db38c508ee73 Signed-off-by: Mazen NEIFER <mazen@nestwave.com>
2017-01-23 00:21:34 +08:00
#if XCHAL_CP_NUM > 0
/* Clear CPENABLE, also in task's co-processor state save area. */
movi a3, 0
xtensa port: Fixed crash on startup on CP enabled cores The issue was that cpStack was changed to a memory buffer by commit https://gerrit.zephyrproject.org/r/#/c/12816 However the assembly code was expecting it to be a pointer and thus issuing an indirection, that leads to wrong addresses. The fix removed this unnecessary indirection and thus the inherent invalid memory access exception. Issue: ZEP-1997 Change-Id: I843f049212f2d116a01b05367a284209f463a5e7 Signed-off-by: Mazen NEIFER <mazen@nestwave.com>
2017-04-14 02:02:49 +08:00
/* a4 = _kernel->current */
Xtensa port: Added Xtensa specific code (C + S) files. Change-Id: I0dff0c33d8577cc70d4d5ee8f298db38c508ee73 Signed-off-by: Mazen NEIFER <mazen@nestwave.com>
2017-01-23 00:21:34 +08:00
wsr a3, CPENABLE
xtensa port: Fixed crash on startup on CP enabled cores The issue was that cpStack was changed to a memory buffer by commit https://gerrit.zephyrproject.org/r/#/c/12816 However the assembly code was expecting it to be a pointer and thus issuing an indirection, that leads to wrong addresses. The fix removed this unnecessary indirection and thus the inherent invalid memory access exception. Issue: ZEP-1997 Change-Id: I843f049212f2d116a01b05367a284209f463a5e7 Signed-off-by: Mazen NEIFER <mazen@nestwave.com>
2017-04-14 02:02:49 +08:00
s16i a3, a4, THREAD_OFFSET(cpEnable) /* clear saved cpenable */
Xtensa port: Added Xtensa specific code (C + S) files. Change-Id: I0dff0c33d8577cc70d4d5ee8f298db38c508ee73 Signed-off-by: Mazen NEIFER <mazen@nestwave.com>
2017-01-23 00:21:34 +08:00
#endif
kernel: event_logger: remove kernel_event_logger Move to more generic tracing hooks that can be implemented in different ways and do not interfere with the kernel. Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2018-04-06 19:48:53 +08:00
#ifdef CONFIG_TRACING
Xtensa port: Added Xtensa specific code (C + S) files. Change-Id: I0dff0c33d8577cc70d4d5ee8f298db38c508ee73 Signed-off-by: Mazen NEIFER <mazen@nestwave.com>
2017-01-23 00:21:34 +08:00
/* Register the context switch */
#ifdef __XTENSA_CALL0_ABI__
systemview: add support natively using tracing hooks Add needed hooks as a subsystem that can be enabled in any application. Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2018-04-06 09:06:33 +08:00
call0 z_sys_trace_thread_switched_in
Xtensa port: Added Xtensa specific code (C + S) files. Change-Id: I0dff0c33d8577cc70d4d5ee8f298db38c508ee73 Signed-off-by: Mazen NEIFER <mazen@nestwave.com>
2017-01-23 00:21:34 +08:00
#else
systemview: add support natively using tracing hooks Add needed hooks as a subsystem that can be enabled in any application. Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2018-04-06 09:06:33 +08:00
call4 z_sys_trace_thread_switched_in
Xtensa port: Added Xtensa specific code (C + S) files. Change-Id: I0dff0c33d8577cc70d4d5ee8f298db38c508ee73 Signed-off-by: Mazen NEIFER <mazen@nestwave.com>
2017-01-23 00:21:34 +08:00
#endif
#endif
Xtensa port: Prevent preemption of locked threads. When an IRQ is serviced, the ISR dispatcher will check for any new thread in the ready queue and switch to it. However, if the current thread is marked as non preemptable due to _kernel.current->base.preempt > _NON_PREEMPT_THRESHOLD then we should not switch to another one. Change-Id: Icdc08105cc6433da479bb95265710462a0f37c0b Signed-off-by: Mazen NEIFER <mazen@nestwave.com>
2017-02-10 05:30:29 +08:00
/* _thread := _kernel.ready_q.cache */
l32i a3, a2, KERNEL_OFFSET(ready_q_cache)
Xtensa port: Added Xtensa specific code (C + S) files. Change-Id: I0dff0c33d8577cc70d4d5ee8f298db38c508ee73 Signed-off-by: Mazen NEIFER <mazen@nestwave.com>
2017-01-23 00:21:34 +08:00
/*
Xtensa port: Removed duplicate code and fixed update of current thread pointer. Having duplicate code leads always to this kind of situation where a bug is fixed in one place and not in the other. This bug of updating current thread pointer was already fixed before in the Swap function, but not in the interrupt handler. Change-Id: I466aea2d35382446c5c82fe775ada31f0bd19492 Signed-off-by: Mazen NEIFER <mazen@nestwave.com>
2017-02-04 01:33:23 +08:00
* Swap threads if any is to be swapped in.
Xtensa port: Added Xtensa specific code (C + S) files. Change-Id: I0dff0c33d8577cc70d4d5ee8f298db38c508ee73 Signed-off-by: Mazen NEIFER <mazen@nestwave.com>
2017-01-23 00:21:34 +08:00
*/
Xtensa port: Prevent preemption of locked threads. When an IRQ is serviced, the ISR dispatcher will check for any new thread in the ready queue and switch to it. However, if the current thread is marked as non preemptable due to _kernel.current->base.preempt > _NON_PREEMPT_THRESHOLD then we should not switch to another one. Change-Id: Icdc08105cc6433da479bb95265710462a0f37c0b Signed-off-by: Mazen NEIFER <mazen@nestwave.com>
2017-02-10 05:30:29 +08:00
call0 _zxt_dispatch /* (_kernel@a2, _thread@a3) */
Xtensa port: Added Xtensa specific code (C + S) files. Change-Id: I0dff0c33d8577cc70d4d5ee8f298db38c508ee73 Signed-off-by: Mazen NEIFER <mazen@nestwave.com>
2017-01-23 00:21:34 +08:00
/* Never reaches here. */