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zephyr/dts/bindings/cpu/cpu.yaml

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dts: bindings: Add bindings for ARM, ARC, Xtensa CPUs This commit adds YAML files providing bindings for the ARM, ARC and Xtensa CPUs. Signed-off-by: Piotr Zięcik <piotr.ziecik@nordicsemi.no>
2019-06-17 22:07:00 +08:00
# Copyright (c) 2019 Nordic Semiconductor ASA
# SPDX-License-Identifier: Apache-2.0
dts: edtlib: Sanity-check the final merged binding only Sanity-checking each !included file separately was inherited from the old scripts. It makes it messy to check that combinations of fields make sense, e.g. to check 'const:' or 'default:' against 'type:', since those fields might come from different files (this is handy, since it makes sense to just add/change a 'const:' value, for example). Drop the requirement that each !included file is a complete binding in itself, and treat them as binding fragments instead. Only check the final merged binding. This also means that !included files no longer need to have a 'description:' or 'title:' (those have always been unused for !included files), so remove those, and add comments that explain what the fragments are for instead. That should demystify bindings a bit. Also fix the descriptions of i2c.yaml, i2s.yaml, spi.yaml, and uart.yaml. They're for controllers, not devices. These are copy-paste error from the corresponding device .yaml files. Piggyback some indentation consistency nits in binding-template.yaml. Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
2019-08-15 20:06:15 +08:00
# Common fields for CPUs
dts: bindings: Add bindings for ARM, ARC, Xtensa CPUs This commit adds YAML files providing bindings for the ARM, ARC and Xtensa CPUs. Signed-off-by: Piotr Zięcik <piotr.ziecik@nordicsemi.no>
2019-06-17 22:07:00 +08:00
dts/bindings: Convert bindings to new include syntax Convert from: inherits: !include spi-device.yaml to: include: spi-device.yaml Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2019-08-22 07:10:12 +08:00
include: base.yaml
dts: bindings: Add bindings for ARM, ARC, Xtensa CPUs This commit adds YAML files providing bindings for the ARM, ARC and Xtensa CPUs. Signed-off-by: Piotr Zięcik <piotr.ziecik@nordicsemi.no>
2019-06-17 22:07:00 +08:00
properties:
clock-frequency:
type: int
dts: bindings: Have 'required: true/false' instead of 'category: ...' The 'category: required/optional' setting for properties is just a yes/no thing. Using a boolean makes it clearer, so have 'required: true/false' instead. Print a clear error when 'category:' is used: edtlib.EDTError: please put 'required: true' instead of 'category: required' in 'properties: foo: ...' in test-bindings/sub-node-parent.yaml - 'category' has been removed The old scripts in scripts/dts/ ignore this setting, and only print a warning if 'category: required' in an inherited binding is changed to 'category: optional'. Remove that code, since the new scripts already have the same check. The replacement was done with git ls-files 'dts/bindings/*.yaml' | xargs sed -i \ -e 's/category:\s*required/required: true/' \ -e 's/category:\s*optional/required: false/' dts/binding-template.yaml is updated as well. Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
2019-08-28 06:22:01 +08:00
required: false
dts: bindings: Add bindings for ARM, ARC, Xtensa CPUs This commit adds YAML files providing bindings for the ARM, ARC and Xtensa CPUs. Signed-off-by: Piotr Zięcik <piotr.ziecik@nordicsemi.no>
2019-06-17 22:07:00 +08:00
description: Clock frequency in Hz
dts: power: Add power states support Add power state property binding and include this property in cpu. The pm-state attribute is a enum that matches with enum pm_state right now the only timing attribute is the minimum residency that is the minimum time for a power state be worthwhile. Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2020-11-26 02:39:43 +08:00
pm-states:
type: phandles
required: false
description: List of power management states supported by this cpu
cache: Expand the APIs for cache flushing The only two supported operations for data caches in the cache framework are currently arch_dcache_flush() and arch_dcache_invd(). This is quite restrictive because for some architectures we also want to control i-cache and in general we want a finer control over what can be flushed, invalidated or cleaned. To address these needs this patch expands the set of operations that can be performed on data and instruction caches, adding hooks for the operations on the whole cache, a specific level or a specific address range. Signed-off-by: Carlo Caione <ccaione@baylibre.com>
2020-12-02 19:38:58 +08:00
i-cache-line-size:
type: int
required: false
description: i-cache line size
default: 0
d-cache-line-size:
type: int
required: false
description: d-cache line size
default: 0