e77c841023
The only two supported operations for data caches in the cache framework are currently arch_dcache_flush() and arch_dcache_invd(). This is quite restrictive because for some architectures we also want to control i-cache and in general we want a finer control over what can be flushed, invalidated or cleaned. To address these needs this patch expands the set of operations that can be performed on data and instruction caches, adding hooks for the operations on the whole cache, a specific level or a specific address range. Signed-off-by: Carlo Caione <ccaione@baylibre.com> |
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| .. | ||
| altr,nios2f.yaml | ||
| arm,cortex-a53.yaml | ||
| arm,cortex-a72.yaml | ||
| arm,cortex-m0+.yaml | ||
| arm,cortex-m0.yaml | ||
| arm,cortex-m1.yaml | ||
| arm,cortex-m3.yaml | ||
| arm,cortex-m4.yaml | ||
| arm,cortex-m4f.yaml | ||
| arm,cortex-m7.yaml | ||
| arm,cortex-m23.yaml | ||
| arm,cortex-m33.yaml | ||
| arm,cortex-m33f.yaml | ||
| arm,cortex-r4.yaml | ||
| arm,cortex-r4f.yaml | ||
| arm,cortex-r5.yaml | ||
| arm,cortex-r5f.yaml | ||
| arm,cortex-r7.yaml | ||
| cadence,tensilica-xtensa-lx4.yaml | ||
| cadence,tensilica-xtensa-lx6.yaml | ||
| cpu.yaml | ||
| qemu,nios2-zephyr.yaml | ||
| riscv,it8xxx2.yaml | ||
| sample_controller.yaml | ||
| snps,arcem.yaml | ||