zephyr/soc/x86/atom/soc.h

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/*
* Copyright (c) 2010-2015, Wind River Systems, Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief Board configuration macros for the ia32 platform
*
* This header file is used to specify and describe board-level aspects for
* the 'ia32' platform.
*/
#ifndef __SOC_H_
#define __SOC_H_
#include <sys/util.h>
#ifndef _ASMLANGUAGE
#include <device.h>
#include <random/rand32.h>
#endif
/*
* UART
*/
arch/x86: early_serial cleanup Various cleanups to the x86 early serial driver, mostly with the goal of simplifying its deployment during board bringup (which is really the only reason it exists in the first place): + Configure it =y by default. While there are surely constrained environments that will want to disable it, this is a TINY driver, and it serves a very important role for niche tasks. It should be built always to make sure it works everywhere. + Decouple from devicetree as much as possible. This code HAS to work during board bringup, often with configurations cribbed from other machines, before proper configuration gets written. Experimentally, devicetree errors tend to be easy to make, and without a working console impossible to diagnose. Specify the device via integer constants in soc.h (in the case of IOPORT access, we already had such a symbol) so that the path from what the developer intends to what the code executes is as short and obvious as possible. Unfortunately I'm not allowed to remove devicetree entirely here, but at least a developer adding a new platform will be able to override it in an obvious way instead of banging blindly on the other side of a DTS compiler. + Don't try to probe the PCI device by ID to "verify". While this sounds like a good idea, in practice it's just an extra thing to get wrong. If we bail on our early console because someone (yes, that's me) got the bus/device/function right but typoed the VID/DID numbers, we're doing no one any favors. + Remove the word-sized-I/O feature. This is a x86 driver for a PCI device. No known PC hardware requires that UART register access be done in dword units (in fact doing so would be a violation of the PCI specifciation as I understand it). It looks to have been cut and pasted from the ns16550 driver, remove. Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2020-06-12 22:59:28 +08:00
#define UART_NS16550_ACCESS_IOPORT 0x3f8
/* PCI definitions */
/* FIXME: The values below copied from generic ia32 soc, we need to get the
* correct numbers for Atom and the minnowboard
*
* This is added now to get basic enumartion of devices and verify that PCI
* driver is functional.
*/
#define PCI_BUS_NUMBERS 1
#define PCI_CTRL_ADDR_REG 0xCF8
#define PCI_CTRL_DATA_REG 0xCFC
#define PCI_INTA 1
#define PCI_INTB 2
#define PCI_INTC 3
#define PCI_INTD 4
/**
*
* @brief Convert PCI interrupt PIN to IRQ
*
* @return IRQ number, -1 if the result is incorrect
*
*/
static inline int pci_pin2irq(int bus, int dev, int pin)
{
ARG_UNUSED(bus);
if ((pin < PCI_INTA) || (pin > PCI_INTD)) {
return -1;
}
return 10 + (((pin + dev - 1) >> 1) & 1);
}
#endif /* __SOC_H_ */