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zephyr/dts/x86/intel/elkhart_lake.dtsi

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soc: x86: Add Elkhart Lake SoC definition Add a basic definition for the Intel Elkhart Lake SoC. Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2020-12-11 02:08:37 +08:00
/*
* Copyright (c) 2020 Intel Corporation.
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "skeleton.dtsi"
dts: migrate includes to <zephyr/...> In order to bring consistency in-tree, migrate all dts code to the new prefix <zephyr/...>. Note that the conversion has been scripted, refer to zephyrproject-rtos#45388 for more details. Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-05-06 17:02:05 +08:00
#include <zephyr/dt-bindings/interrupt-controller/intel-ioapic.h>
#include <zephyr/dt-bindings/i2c/i2c.h>
#include <zephyr/dt-bindings/pcie/pcie.h>
soc: x86: Add Elkhart Lake SoC definition Add a basic definition for the Intel Elkhart Lake SoC. Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2020-12-11 02:08:37 +08:00
/ {
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
x86: Add intel,x86_64 compat to all x86-64 platforms This will help distinguish 64 and 32-bit platforms by tooling, following the pattern visible in e.g. RISC-V. Signed-off-by: Piotr Zierhoffer <pzierhoffer@antmicro.com> Signed-off-by: Mateusz Hołenko <mholenko@antmicro.com>
2024-09-16 21:03:27 +08:00
compatible = "intel,elkhart-lake", "intel,x86_64";
dts/x86: Add cache line size There is a property for it so let's use it. Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2021-02-11 16:42:44 +08:00
d-cache-line-size = <64>;
soc: x86: Add Elkhart Lake SoC definition Add a basic definition for the Intel Elkhart Lake SoC. Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2020-12-11 02:08:37 +08:00
reg = <0>;
};
};
dram0: memory@0 {
device_type = "memory";
reg = <0x0 DT_DRAM_SIZE>;
};
edac: Move IBECC information to DT root Move EDAC/IBECC data to Device Tree root. Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
2021-01-25 23:04:03 +08:00
ibecc: ibecc {
dts: cleanup leading spaces Cleanup leading spaces found via the following regexes: r" compatible =" r"^ " in: zephyr/**/*.dts zephyr/**/*.dtsi Signed-off-by: Jordan Yates <jordan@embeint.com>
2024-06-20 11:29:03 +08:00
compatible = "intel,ibecc";
status = "okay";
edac: Move IBECC information to DT root Move EDAC/IBECC data to Device Tree root. Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
2021-01-25 23:04:03 +08:00
};
soc: x86: Add Elkhart Lake SoC definition Add a basic definition for the Intel Elkhart Lake SoC. Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2020-12-11 02:08:37 +08:00
intc: ioapic@fec00000 {
compatible = "intel,ioapic";
boards: intel: Fix Missing #address-cells warning Specify properties to fix compile warning: Warning (interrupt_provider): /ioapic@fec00000: Missing #address-cells in interrupt provider Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
2023-08-17 22:23:08 +08:00
#address-cells = <1>;
#interrupt-cells = <3>;
soc: x86: Add Elkhart Lake SoC definition Add a basic definition for the Intel Elkhart Lake SoC. Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2020-12-11 02:08:37 +08:00
reg = <0xfec00000 0x1000>;
interrupt-controller;
};
drivers: loapic: add device tree support for loapic As per #26393, Local APIC is using Kconfig based option for the base address. This patch adds DTS binding support in the driver, just like its conunter part I/O APIC. Signed-off-by: Umar Nisar <umar.nisar@intel.com>
2023-07-07 04:27:04 +08:00
intc_loapic: loapic@fee00000 {
compatible = "intel,loapic";
reg = <0xfee00000 0x1000>;
interrupt-controller;
#interrupt-cells = <3>;
#address-cells = <1>;
};
board: *_x86: Allow pcie0 to be referenced Changing pcie0 to pcie0: pcie0 allows it to be referenced as &pcie0. I am not sure why this is required. Otherwise I get error: ... parse error: undefined node label 'pcie0' ... Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
2022-11-21 18:23:22 +08:00
pcie0: pcie0 {
soc: x86: Add Elkhart Lake SoC definition Add a basic definition for the Intel Elkhart Lake SoC. Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2020-12-11 02:08:37 +08:00
#address-cells = <1>;
#size-cells = <1>;
boards: x86: add pci controller node with acpi pnp id add acpi pnp/hw id for pcie node to enable support for retreive interrupt routing information for pci legacy interrupt via acpi Signed-off-by: Najumon B.A <najumon.ba@intel.com>
2023-10-31 21:54:38 +08:00
compatible = "pcie-controller";
acpi-hid = "PNP0A08";
soc: x86: Add Elkhart Lake SoC definition Add a basic definition for the Intel Elkhart Lake SoC. Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2020-12-11 02:08:37 +08:00
ranges;
drivers: pci: ptm: Convert to use dynamic BDF lookup Use the new PCIe core infrastructure for looking up the BDF at runtime based on the VID/DID values. Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2022-11-11 18:20:23 +08:00
ptm_root0: ptm_root0 {
dts/x86: Enable PTM root device Port 0 exposes such capability. Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2021-09-07 17:51:22 +08:00
compatible = "ptm-root";
drivers: pci: ptm: Convert to use dynamic BDF lookup Use the new PCIe core infrastructure for looking up the BDF at runtime based on the VID/DID values. Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2022-11-11 18:20:23 +08:00
vendor-id = <0x8086>;
device-id = <0x4b38>;
dts/x86: Enable PTM root device Port 0 exposes such capability. Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2021-09-07 17:51:22 +08:00
status = "okay";
};
drivers: uart_ns16550: Convert to use runtime PCIe BDF lookup Convert the ns16550 driver to use the new centralized runtime BDF lookup of PCIe devices. Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2022-11-09 19:21:47 +08:00
uart0: uart0 {
soc: x86: Add Elkhart Lake SoC definition Add a basic definition for the Intel Elkhart Lake SoC. Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2020-12-11 02:08:37 +08:00
compatible = "ns16550";
drivers: uart_ns16550: Convert to use runtime PCIe BDF lookup Convert the ns16550 driver to use the new centralized runtime BDF lookup of PCIe devices. Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2022-11-09 19:21:47 +08:00
vendor-id = <0x8086>;
device-id = <0x4b28>;
soc: x86: Add Elkhart Lake SoC definition Add a basic definition for the Intel Elkhart Lake SoC. Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2020-12-11 02:08:37 +08:00
drivers: uart_ns16550: Convert to use runtime PCIe BDF lookup Convert the ns16550 driver to use the new centralized runtime BDF lookup of PCIe devices. Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2022-11-09 19:21:47 +08:00
reg-shift = <2>;
soc: x86: Add Elkhart Lake SoC definition Add a basic definition for the Intel Elkhart Lake SoC. Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2020-12-11 02:08:37 +08:00
clock-frequency = <1843200>;
interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
interrupt-parent = <&intc>;
status = "okay";
current-speed = <115200>;
};
drivers: uart_ns16550: Convert to use runtime PCIe BDF lookup Convert the ns16550 driver to use the new centralized runtime BDF lookup of PCIe devices. Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2022-11-09 19:21:47 +08:00
uart1: uart1 {
soc: x86: Add Elkhart Lake SoC definition Add a basic definition for the Intel Elkhart Lake SoC. Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2020-12-11 02:08:37 +08:00
compatible = "ns16550";
drivers: uart_ns16550: Convert to use runtime PCIe BDF lookup Convert the ns16550 driver to use the new centralized runtime BDF lookup of PCIe devices. Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2022-11-09 19:21:47 +08:00
vendor-id = <0x8086>;
device-id = <0x4b29>;
soc: x86: Add Elkhart Lake SoC definition Add a basic definition for the Intel Elkhart Lake SoC. Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2020-12-11 02:08:37 +08:00
drivers: uart_ns16550: Convert to use runtime PCIe BDF lookup Convert the ns16550 driver to use the new centralized runtime BDF lookup of PCIe devices. Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2022-11-09 19:21:47 +08:00
reg-shift = <2>;
soc: x86: Add Elkhart Lake SoC definition Add a basic definition for the Intel Elkhart Lake SoC. Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2020-12-11 02:08:37 +08:00
clock-frequency = <1843200>;
interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
interrupt-parent = <&intc>;
status = "okay";
current-speed = <115200>;
};
drivers: uart_ns16550: Convert to use runtime PCIe BDF lookup Convert the ns16550 driver to use the new centralized runtime BDF lookup of PCIe devices. Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2022-11-09 19:21:47 +08:00
uart2: uart2 {
soc: x86: Add Elkhart Lake SoC definition Add a basic definition for the Intel Elkhart Lake SoC. Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2020-12-11 02:08:37 +08:00
compatible = "ns16550";
drivers: uart_ns16550: Convert to use runtime PCIe BDF lookup Convert the ns16550 driver to use the new centralized runtime BDF lookup of PCIe devices. Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2022-11-09 19:21:47 +08:00
vendor-id = <0x8086>;
device-id = <0x4b4d>;
soc: x86: Add Elkhart Lake SoC definition Add a basic definition for the Intel Elkhart Lake SoC. Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2020-12-11 02:08:37 +08:00
drivers: uart_ns16550: Convert to use runtime PCIe BDF lookup Convert the ns16550 driver to use the new centralized runtime BDF lookup of PCIe devices. Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2022-11-09 19:21:47 +08:00
reg-shift = <2>;
soc: x86: Add Elkhart Lake SoC definition Add a basic definition for the Intel Elkhart Lake SoC. Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2020-12-11 02:08:37 +08:00
clock-frequency = <1843200>;
interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
interrupt-parent = <&intc>;
status = "okay";
current-speed = <115200>;
};
drivers: uart_ns16550: Convert to use runtime PCIe BDF lookup Convert the ns16550 driver to use the new centralized runtime BDF lookup of PCIe devices. Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2022-11-09 19:21:47 +08:00
uart_pse_0: uart_pse_0 {
soc: x86: Add Elkhart Lake SoC definition Add a basic definition for the Intel Elkhart Lake SoC. Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2020-12-11 02:08:37 +08:00
compatible = "ns16550";
drivers: uart_ns16550: Convert to use runtime PCIe BDF lookup Convert the ns16550 driver to use the new centralized runtime BDF lookup of PCIe devices. Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2022-11-09 19:21:47 +08:00
vendor-id = <0x8086>;
device-id = <0x4b96>;
soc: x86: Add Elkhart Lake SoC definition Add a basic definition for the Intel Elkhart Lake SoC. Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2020-12-11 02:08:37 +08:00
drivers: uart_ns16550: Convert to use runtime PCIe BDF lookup Convert the ns16550 driver to use the new centralized runtime BDF lookup of PCIe devices. Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2022-11-09 19:21:47 +08:00
reg-shift = <2>;
soc: x86: Add Elkhart Lake SoC definition Add a basic definition for the Intel Elkhart Lake SoC. Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2020-12-11 02:08:37 +08:00
clock-frequency = <1843200>;
interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
interrupt-parent = <&intc>;
soc: x86: elkhart_lake: Update UART definitions Add definitions for UART1/2 when they're accessible through fixed MMIO addresses (instead of PCIe), and mark all UARTs not normally available with the UEFI BIOS as "disabled". Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2020-12-21 22:24:15 +08:00
status = "disabled";
soc: x86: Add Elkhart Lake SoC definition Add a basic definition for the Intel Elkhart Lake SoC. Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2020-12-11 02:08:37 +08:00
current-speed = <115200>;
};
drivers: uart_ns16550: Convert to use runtime PCIe BDF lookup Convert the ns16550 driver to use the new centralized runtime BDF lookup of PCIe devices. Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2022-11-09 19:21:47 +08:00
uart_pse_1: uart_pse_1 {
soc: x86: Add Elkhart Lake SoC definition Add a basic definition for the Intel Elkhart Lake SoC. Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2020-12-11 02:08:37 +08:00
compatible = "ns16550";
drivers: uart_ns16550: Convert to use runtime PCIe BDF lookup Convert the ns16550 driver to use the new centralized runtime BDF lookup of PCIe devices. Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2022-11-09 19:21:47 +08:00
vendor-id = <0x8086>;
device-id = <0x4b97>;
soc: x86: Add Elkhart Lake SoC definition Add a basic definition for the Intel Elkhart Lake SoC. Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2020-12-11 02:08:37 +08:00
drivers: uart_ns16550: Convert to use runtime PCIe BDF lookup Convert the ns16550 driver to use the new centralized runtime BDF lookup of PCIe devices. Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2022-11-09 19:21:47 +08:00
reg-shift = <2>;
soc: x86: Add Elkhart Lake SoC definition Add a basic definition for the Intel Elkhart Lake SoC. Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2020-12-11 02:08:37 +08:00
clock-frequency = <1843200>;
interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
interrupt-parent = <&intc>;
soc: x86: elkhart_lake: Update UART definitions Add definitions for UART1/2 when they're accessible through fixed MMIO addresses (instead of PCIe), and mark all UARTs not normally available with the UEFI BIOS as "disabled". Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2020-12-21 22:24:15 +08:00
status = "disabled";
soc: x86: Add Elkhart Lake SoC definition Add a basic definition for the Intel Elkhart Lake SoC. Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2020-12-11 02:08:37 +08:00
current-speed = <115200>;
};
drivers: uart_ns16550: Convert to use runtime PCIe BDF lookup Convert the ns16550 driver to use the new centralized runtime BDF lookup of PCIe devices. Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2022-11-09 19:21:47 +08:00
uart_pse_2: uart_pse_2 {
soc: x86: Add Elkhart Lake SoC definition Add a basic definition for the Intel Elkhart Lake SoC. Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2020-12-11 02:08:37 +08:00
compatible = "ns16550";
drivers: uart_ns16550: Convert to use runtime PCIe BDF lookup Convert the ns16550 driver to use the new centralized runtime BDF lookup of PCIe devices. Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2022-11-09 19:21:47 +08:00
vendor-id = <0x8086>;
device-id = <0x4b98>;
soc: x86: Add Elkhart Lake SoC definition Add a basic definition for the Intel Elkhart Lake SoC. Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2020-12-11 02:08:37 +08:00
drivers: uart_ns16550: Convert to use runtime PCIe BDF lookup Convert the ns16550 driver to use the new centralized runtime BDF lookup of PCIe devices. Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2022-11-09 19:21:47 +08:00
reg-shift = <2>;
soc: x86: Add Elkhart Lake SoC definition Add a basic definition for the Intel Elkhart Lake SoC. Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2020-12-11 02:08:37 +08:00
clock-frequency = <1843200>;
interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
interrupt-parent = <&intc>;
soc: x86: elkhart_lake: Update UART definitions Add definitions for UART1/2 when they're accessible through fixed MMIO addresses (instead of PCIe), and mark all UARTs not normally available with the UEFI BIOS as "disabled". Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2020-12-21 22:24:15 +08:00
status = "disabled";
soc: x86: Add Elkhart Lake SoC definition Add a basic definition for the Intel Elkhart Lake SoC. Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2020-12-11 02:08:37 +08:00
current-speed = <115200>;
};
drivers: uart_ns16550: Convert to use runtime PCIe BDF lookup Convert the ns16550 driver to use the new centralized runtime BDF lookup of PCIe devices. Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2022-11-09 19:21:47 +08:00
uart_pse_3: uart_pse_3 {
soc: x86: Add Elkhart Lake SoC definition Add a basic definition for the Intel Elkhart Lake SoC. Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2020-12-11 02:08:37 +08:00
compatible = "ns16550";
drivers: uart_ns16550: Convert to use runtime PCIe BDF lookup Convert the ns16550 driver to use the new centralized runtime BDF lookup of PCIe devices. Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2022-11-09 19:21:47 +08:00
vendor-id = <0x8086>;
device-id = <0x4b99>;
soc: x86: Add Elkhart Lake SoC definition Add a basic definition for the Intel Elkhart Lake SoC. Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2020-12-11 02:08:37 +08:00
drivers: uart_ns16550: Convert to use runtime PCIe BDF lookup Convert the ns16550 driver to use the new centralized runtime BDF lookup of PCIe devices. Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2022-11-09 19:21:47 +08:00
reg-shift = <2>;
soc: x86: Add Elkhart Lake SoC definition Add a basic definition for the Intel Elkhart Lake SoC. Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2020-12-11 02:08:37 +08:00
clock-frequency = <1843200>;
interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
interrupt-parent = <&intc>;
soc: x86: elkhart_lake: Update UART definitions Add definitions for UART1/2 when they're accessible through fixed MMIO addresses (instead of PCIe), and mark all UARTs not normally available with the UEFI BIOS as "disabled". Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2020-12-21 22:24:15 +08:00
status = "disabled";
soc: x86: Add Elkhart Lake SoC definition Add a basic definition for the Intel Elkhart Lake SoC. Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2020-12-11 02:08:37 +08:00
current-speed = <115200>;
};
drivers: uart_ns16550: Convert to use runtime PCIe BDF lookup Convert the ns16550 driver to use the new centralized runtime BDF lookup of PCIe devices. Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2022-11-09 19:21:47 +08:00
uart_pse_4: uart_pse_4 {
soc: x86: Add Elkhart Lake SoC definition Add a basic definition for the Intel Elkhart Lake SoC. Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2020-12-11 02:08:37 +08:00
compatible = "ns16550";
drivers: uart_ns16550: Convert to use runtime PCIe BDF lookup Convert the ns16550 driver to use the new centralized runtime BDF lookup of PCIe devices. Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2022-11-09 19:21:47 +08:00
vendor-id = <0x8086>;
device-id = <0x4b9a>;
soc: x86: Add Elkhart Lake SoC definition Add a basic definition for the Intel Elkhart Lake SoC. Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2020-12-11 02:08:37 +08:00
drivers: uart_ns16550: Convert to use runtime PCIe BDF lookup Convert the ns16550 driver to use the new centralized runtime BDF lookup of PCIe devices. Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2022-11-09 19:21:47 +08:00
reg-shift = <2>;
soc: x86: Add Elkhart Lake SoC definition Add a basic definition for the Intel Elkhart Lake SoC. Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2020-12-11 02:08:37 +08:00
clock-frequency = <1843200>;
interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
interrupt-parent = <&intc>;
soc: x86: elkhart_lake: Update UART definitions Add definitions for UART1/2 when they're accessible through fixed MMIO addresses (instead of PCIe), and mark all UARTs not normally available with the UEFI BIOS as "disabled". Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2020-12-21 22:24:15 +08:00
status = "disabled";
soc: x86: Add Elkhart Lake SoC definition Add a basic definition for the Intel Elkhart Lake SoC. Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2020-12-11 02:08:37 +08:00
current-speed = <115200>;
};
drivers: uart_ns16550: Convert to use runtime PCIe BDF lookup Convert the ns16550 driver to use the new centralized runtime BDF lookup of PCIe devices. Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2022-11-09 19:21:47 +08:00
uart_pse_5: uart_pse_5 {
soc: x86: Add Elkhart Lake SoC definition Add a basic definition for the Intel Elkhart Lake SoC. Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2020-12-11 02:08:37 +08:00
compatible = "ns16550";
drivers: uart_ns16550: Convert to use runtime PCIe BDF lookup Convert the ns16550 driver to use the new centralized runtime BDF lookup of PCIe devices. Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2022-11-09 19:21:47 +08:00
vendor-id = <0x8086>;
device-id = <0x4b9b>;
soc: x86: Add Elkhart Lake SoC definition Add a basic definition for the Intel Elkhart Lake SoC. Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2020-12-11 02:08:37 +08:00
drivers: uart_ns16550: Convert to use runtime PCIe BDF lookup Convert the ns16550 driver to use the new centralized runtime BDF lookup of PCIe devices. Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2022-11-09 19:21:47 +08:00
reg-shift = <2>;
soc: x86: Add Elkhart Lake SoC definition Add a basic definition for the Intel Elkhart Lake SoC. Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2020-12-11 02:08:37 +08:00
clock-frequency = <1843200>;
interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
interrupt-parent = <&intc>;
soc: x86: elkhart_lake: Update UART definitions Add definitions for UART1/2 when they're accessible through fixed MMIO addresses (instead of PCIe), and mark all UARTs not normally available with the UEFI BIOS as "disabled". Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2020-12-21 22:24:15 +08:00
status = "disabled";
soc: x86: Add Elkhart Lake SoC definition Add a basic definition for the Intel Elkhart Lake SoC. Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2020-12-11 02:08:37 +08:00
current-speed = <115200>;
};
soc: x86: elkhart_lake: Update UART definitions Add definitions for UART1/2 when they're accessible through fixed MMIO addresses (instead of PCIe), and mark all UARTs not normally available with the UEFI BIOS as "disabled". Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2020-12-21 22:24:15 +08:00
smbus: Convert to use runtime BDF lookup Convert PCH SMBus driver, tests and samples to use new dynamic BDF lookup. Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
2022-11-17 21:35:09 +08:00
smbus0: smbus0 {
board: elkhart_lake: Add smbus to the board's DTS Add PCH SMBus to Elkhart Lake device tree. Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
2022-08-12 22:27:21 +08:00
compatible = "intel,pch-smbus";
#address-cells = <1>;
#size-cells = <0>;
smbus: Convert to use runtime BDF lookup Convert PCH SMBus driver, tests and samples to use new dynamic BDF lookup. Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
2022-11-17 21:35:09 +08:00
vendor-id = <0x8086>;
device-id = <0x4b23>;
boards: x86: Detect SMBus IRQ instead of hardcoding Detect IRQ for SMBus instead of hardcoding. Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
2023-09-26 18:55:56 +08:00
interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
board: elkhart_lake: Add smbus to the board's DTS Add PCH SMBus to Elkhart Lake device tree. Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
2022-08-12 22:27:21 +08:00
interrupt-parent = <&intc>;
status = "okay";
};
drivers: i2c_dw: Convert to use dynamic BDF lookup Use the new PCIe core infrastructure for looking up the BDF at runtime based on the VID/DID values. Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2022-11-11 16:36:44 +08:00
i2c0: i2c0 {
soc: x86: Add Elkhart Lake SoC definition Add a basic definition for the Intel Elkhart Lake SoC. Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2020-12-11 02:08:37 +08:00
compatible = "snps,designware-i2c";
clock-frequency = <I2C_BITRATE_STANDARD>;
#address-cells = <1>;
#size-cells = <0>;
drivers: i2c_dw: Convert to use dynamic BDF lookup Use the new PCIe core infrastructure for looking up the BDF at runtime based on the VID/DID values. Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2022-11-11 16:36:44 +08:00
vendor-id = <0x8086>;
device-id = <0x4b78>;
soc: x86: Add Elkhart Lake SoC definition Add a basic definition for the Intel Elkhart Lake SoC. Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2020-12-11 02:08:37 +08:00
interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
interrupt-parent = <&intc>;
status = "okay";
};
drivers: i2c_dw: Convert to use dynamic BDF lookup Use the new PCIe core infrastructure for looking up the BDF at runtime based on the VID/DID values. Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2022-11-11 16:36:44 +08:00
i2c1: i2c1 {
soc: x86: Add Elkhart Lake SoC definition Add a basic definition for the Intel Elkhart Lake SoC. Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2020-12-11 02:08:37 +08:00
compatible = "snps,designware-i2c";
clock-frequency = <I2C_BITRATE_STANDARD>;
#address-cells = <1>;
#size-cells = <0>;
drivers: i2c_dw: Convert to use dynamic BDF lookup Use the new PCIe core infrastructure for looking up the BDF at runtime based on the VID/DID values. Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2022-11-11 16:36:44 +08:00
vendor-id = <0x8086>;
device-id = <0x4b79>;
soc: x86: Add Elkhart Lake SoC definition Add a basic definition for the Intel Elkhart Lake SoC. Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2020-12-11 02:08:37 +08:00
interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
interrupt-parent = <&intc>;
status = "okay";
};
drivers: i2c_dw: Convert to use dynamic BDF lookup Use the new PCIe core infrastructure for looking up the BDF at runtime based on the VID/DID values. Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2022-11-11 16:36:44 +08:00
i2c2: i2c2 {
soc: x86: Add Elkhart Lake SoC definition Add a basic definition for the Intel Elkhart Lake SoC. Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2020-12-11 02:08:37 +08:00
compatible = "snps,designware-i2c";
clock-frequency = <I2C_BITRATE_STANDARD>;
#address-cells = <1>;
#size-cells = <0>;
drivers: i2c_dw: Convert to use dynamic BDF lookup Use the new PCIe core infrastructure for looking up the BDF at runtime based on the VID/DID values. Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2022-11-11 16:36:44 +08:00
vendor-id = <0x8086>;
device-id = <0x4b7a>;
soc: x86: Add Elkhart Lake SoC definition Add a basic definition for the Intel Elkhart Lake SoC. Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2020-12-11 02:08:37 +08:00
interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
interrupt-parent = <&intc>;
status = "okay";
};
drivers: i2c_dw: Convert to use dynamic BDF lookup Use the new PCIe core infrastructure for looking up the BDF at runtime based on the VID/DID values. Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2022-11-11 16:36:44 +08:00
i2c3: i2c3 {
soc: x86: Add Elkhart Lake SoC definition Add a basic definition for the Intel Elkhart Lake SoC. Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2020-12-11 02:08:37 +08:00
compatible = "snps,designware-i2c";
clock-frequency = <I2C_BITRATE_STANDARD>;
#address-cells = <1>;
#size-cells = <0>;
drivers: i2c_dw: Convert to use dynamic BDF lookup Use the new PCIe core infrastructure for looking up the BDF at runtime based on the VID/DID values. Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2022-11-11 16:36:44 +08:00
vendor-id = <0x8086>;
device-id = <0x4b7b>;
soc: x86: Add Elkhart Lake SoC definition Add a basic definition for the Intel Elkhart Lake SoC. Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2020-12-11 02:08:37 +08:00
interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
interrupt-parent = <&intc>;
status = "okay";
};
drivers: i2c_dw: Convert to use dynamic BDF lookup Use the new PCIe core infrastructure for looking up the BDF at runtime based on the VID/DID values. Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2022-11-11 16:36:44 +08:00
i2c4: i2c4 {
soc: x86: Add Elkhart Lake SoC definition Add a basic definition for the Intel Elkhart Lake SoC. Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2020-12-11 02:08:37 +08:00
compatible = "snps,designware-i2c";
clock-frequency = <I2C_BITRATE_STANDARD>;
#address-cells = <1>;
#size-cells = <0>;
drivers: i2c_dw: Convert to use dynamic BDF lookup Use the new PCIe core infrastructure for looking up the BDF at runtime based on the VID/DID values. Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2022-11-11 16:36:44 +08:00
vendor-id = <0x8086>;
device-id = <0x4b4b>;
soc: x86: Add Elkhart Lake SoC definition Add a basic definition for the Intel Elkhart Lake SoC. Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2020-12-11 02:08:37 +08:00
interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
interrupt-parent = <&intc>;
status = "okay";
};
drivers: i2c_dw: Convert to use dynamic BDF lookup Use the new PCIe core infrastructure for looking up the BDF at runtime based on the VID/DID values. Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2022-11-11 16:36:44 +08:00
i2c5: i2c5 {
soc: x86: Add Elkhart Lake SoC definition Add a basic definition for the Intel Elkhart Lake SoC. Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2020-12-11 02:08:37 +08:00
compatible = "snps,designware-i2c";
clock-frequency = <I2C_BITRATE_STANDARD>;
#address-cells = <1>;
#size-cells = <0>;
drivers: i2c_dw: Convert to use dynamic BDF lookup Use the new PCIe core infrastructure for looking up the BDF at runtime based on the VID/DID values. Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2022-11-11 16:36:44 +08:00
vendor-id = <0x8086>;
device-id = <0x4b4c>;
soc: x86: Add Elkhart Lake SoC definition Add a basic definition for the Intel Elkhart Lake SoC. Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2020-12-11 02:08:37 +08:00
interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
interrupt-parent = <&intc>;
status = "okay";
};
drivers: i2c_dw: Convert to use dynamic BDF lookup Use the new PCIe core infrastructure for looking up the BDF at runtime based on the VID/DID values. Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2022-11-11 16:36:44 +08:00
i2c6: i2c6 {
soc: x86: Add Elkhart Lake SoC definition Add a basic definition for the Intel Elkhart Lake SoC. Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2020-12-11 02:08:37 +08:00
compatible = "snps,designware-i2c";
clock-frequency = <I2C_BITRATE_STANDARD>;
#address-cells = <1>;
#size-cells = <0>;
drivers: i2c_dw: Convert to use dynamic BDF lookup Use the new PCIe core infrastructure for looking up the BDF at runtime based on the VID/DID values. Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2022-11-11 16:36:44 +08:00
vendor-id = <0x8086>;
device-id = <0x4b44>;
soc: x86: Add Elkhart Lake SoC definition Add a basic definition for the Intel Elkhart Lake SoC. Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2020-12-11 02:08:37 +08:00
interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
interrupt-parent = <&intc>;
status = "okay";
};
drivers: i2c_dw: Convert to use dynamic BDF lookup Use the new PCIe core infrastructure for looking up the BDF at runtime based on the VID/DID values. Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2022-11-11 16:36:44 +08:00
i2c7: i2c7 {
soc: x86: Add Elkhart Lake SoC definition Add a basic definition for the Intel Elkhart Lake SoC. Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2020-12-11 02:08:37 +08:00
compatible = "snps,designware-i2c";
clock-frequency = <I2C_BITRATE_STANDARD>;
#address-cells = <1>;
#size-cells = <0>;
drivers: i2c_dw: Convert to use dynamic BDF lookup Use the new PCIe core infrastructure for looking up the BDF at runtime based on the VID/DID values. Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2022-11-11 16:36:44 +08:00
vendor-id = <0x8086>;
device-id = <0x4b45>;
soc: x86: Add Elkhart Lake SoC definition Add a basic definition for the Intel Elkhart Lake SoC. Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2020-12-11 02:08:37 +08:00
interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
interrupt-parent = <&intc>;
status = "okay";
};
drivers: i2c_dw: Convert to use dynamic BDF lookup Use the new PCIe core infrastructure for looking up the BDF at runtime based on the VID/DID values. Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2022-11-11 16:36:44 +08:00
i2c_pse_0: i2c_pse_0 {
soc: x86: Add Elkhart Lake SoC definition Add a basic definition for the Intel Elkhart Lake SoC. Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2020-12-11 02:08:37 +08:00
compatible = "snps,designware-i2c";
clock-frequency = <I2C_BITRATE_STANDARD>;
#address-cells = <1>;
#size-cells = <0>;
drivers: i2c_dw: Convert to use dynamic BDF lookup Use the new PCIe core infrastructure for looking up the BDF at runtime based on the VID/DID values. Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2022-11-11 16:36:44 +08:00
vendor-id = <0x8086>;
device-id = <0x4bb9>;
soc: x86: Add Elkhart Lake SoC definition Add a basic definition for the Intel Elkhart Lake SoC. Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2020-12-11 02:08:37 +08:00
interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
interrupt-parent = <&intc>;
status = "okay";
};
drivers: i2c_dw: Convert to use dynamic BDF lookup Use the new PCIe core infrastructure for looking up the BDF at runtime based on the VID/DID values. Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2022-11-11 16:36:44 +08:00
i2c_pse_1: i2c_pse_1 {
soc: x86: Add Elkhart Lake SoC definition Add a basic definition for the Intel Elkhart Lake SoC. Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2020-12-11 02:08:37 +08:00
compatible = "snps,designware-i2c";
clock-frequency = <I2C_BITRATE_STANDARD>;
#address-cells = <1>;
#size-cells = <0>;
drivers: i2c_dw: Convert to use dynamic BDF lookup Use the new PCIe core infrastructure for looking up the BDF at runtime based on the VID/DID values. Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2022-11-11 16:36:44 +08:00
vendor-id = <0x8086>;
device-id = <0x4bba>;
soc: x86: Add Elkhart Lake SoC definition Add a basic definition for the Intel Elkhart Lake SoC. Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2020-12-11 02:08:37 +08:00
interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
interrupt-parent = <&intc>;
status = "okay";
};
drivers: i2c_dw: Convert to use dynamic BDF lookup Use the new PCIe core infrastructure for looking up the BDF at runtime based on the VID/DID values. Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2022-11-11 16:36:44 +08:00
i2c_pse_2: i2c_pse_2 {
soc: x86: Add Elkhart Lake SoC definition Add a basic definition for the Intel Elkhart Lake SoC. Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2020-12-11 02:08:37 +08:00
compatible = "snps,designware-i2c";
clock-frequency = <I2C_BITRATE_STANDARD>;
#address-cells = <1>;
#size-cells = <0>;
drivers: i2c_dw: Convert to use dynamic BDF lookup Use the new PCIe core infrastructure for looking up the BDF at runtime based on the VID/DID values. Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2022-11-11 16:36:44 +08:00
vendor-id = <0x8086>;
device-id = <0x4bbb>;
soc: x86: Add Elkhart Lake SoC definition Add a basic definition for the Intel Elkhart Lake SoC. Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2020-12-11 02:08:37 +08:00
interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
interrupt-parent = <&intc>;
status = "okay";
};
drivers: i2c_dw: Convert to use dynamic BDF lookup Use the new PCIe core infrastructure for looking up the BDF at runtime based on the VID/DID values. Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2022-11-11 16:36:44 +08:00
i2c_pse_3: i2c_pse_3 {
soc: x86: Add Elkhart Lake SoC definition Add a basic definition for the Intel Elkhart Lake SoC. Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2020-12-11 02:08:37 +08:00
compatible = "snps,designware-i2c";
clock-frequency = <I2C_BITRATE_STANDARD>;
#address-cells = <1>;
#size-cells = <0>;
drivers: i2c_dw: Convert to use dynamic BDF lookup Use the new PCIe core infrastructure for looking up the BDF at runtime based on the VID/DID values. Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2022-11-11 16:36:44 +08:00
vendor-id = <0x8086>;
device-id = <0x4bbc>;
soc: x86: Add Elkhart Lake SoC definition Add a basic definition for the Intel Elkhart Lake SoC. Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2020-12-11 02:08:37 +08:00
interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
interrupt-parent = <&intc>;
status = "okay";
};
drivers: i2c_dw: Convert to use dynamic BDF lookup Use the new PCIe core infrastructure for looking up the BDF at runtime based on the VID/DID values. Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2022-11-11 16:36:44 +08:00
i2c_pse_4: i2c_pse_4 {
soc: x86: Add Elkhart Lake SoC definition Add a basic definition for the Intel Elkhart Lake SoC. Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2020-12-11 02:08:37 +08:00
compatible = "snps,designware-i2c";
clock-frequency = <I2C_BITRATE_STANDARD>;
#address-cells = <1>;
#size-cells = <0>;
drivers: i2c_dw: Convert to use dynamic BDF lookup Use the new PCIe core infrastructure for looking up the BDF at runtime based on the VID/DID values. Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2022-11-11 16:36:44 +08:00
vendor-id = <0x8086>;
device-id = <0x4bbd>;
soc: x86: Add Elkhart Lake SoC definition Add a basic definition for the Intel Elkhart Lake SoC. Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2020-12-11 02:08:37 +08:00
interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
interrupt-parent = <&intc>;
status = "okay";
};
drivers: i2c_dw: Convert to use dynamic BDF lookup Use the new PCIe core infrastructure for looking up the BDF at runtime based on the VID/DID values. Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2022-11-11 16:36:44 +08:00
i2c_pse_5: i2c_pse_5 {
soc: x86: Add Elkhart Lake SoC definition Add a basic definition for the Intel Elkhart Lake SoC. Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2020-12-11 02:08:37 +08:00
compatible = "snps,designware-i2c";
clock-frequency = <I2C_BITRATE_STANDARD>;
#address-cells = <1>;
#size-cells = <0>;
drivers: i2c_dw: Convert to use dynamic BDF lookup Use the new PCIe core infrastructure for looking up the BDF at runtime based on the VID/DID values. Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2022-11-11 16:36:44 +08:00
vendor-id = <0x8086>;
device-id = <0x4bbe>;
soc: x86: Add Elkhart Lake SoC definition Add a basic definition for the Intel Elkhart Lake SoC. Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2020-12-11 02:08:37 +08:00
interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
interrupt-parent = <&intc>;
status = "okay";
};
drivers: i2c_dw: Convert to use dynamic BDF lookup Use the new PCIe core infrastructure for looking up the BDF at runtime based on the VID/DID values. Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2022-11-11 16:36:44 +08:00
i2c_pse_6: i2c_pse_6 {
soc: x86: Add Elkhart Lake SoC definition Add a basic definition for the Intel Elkhart Lake SoC. Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2020-12-11 02:08:37 +08:00
compatible = "snps,designware-i2c";
clock-frequency = <I2C_BITRATE_STANDARD>;
#address-cells = <1>;
#size-cells = <0>;
drivers: i2c_dw: Convert to use dynamic BDF lookup Use the new PCIe core infrastructure for looking up the BDF at runtime based on the VID/DID values. Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2022-11-11 16:36:44 +08:00
vendor-id = <0x8086>;
device-id = <0x4bbf>;
soc: x86: Add Elkhart Lake SoC definition Add a basic definition for the Intel Elkhart Lake SoC. Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2020-12-11 02:08:37 +08:00
interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
interrupt-parent = <&intc>;
status = "okay";
};
drivers: i2c_dw: User proper PCIe DT hierarchy Move all PCIe-based DT nodes under a PCIe bus and take advantage of the DT_ANY_INST_ON_BUS_STATUS_OKAY() and DT_INST_ON_BUS() macros. Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2021-01-19 18:46:43 +08:00
};
soc {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
ranges;
dts/x86: Add VT-D node on Elkhart Lake Kconfig options will anyway enable/disable the driver relevantly. Signed-off-by: Jukka Rissanen <jukka.rissanen@linux.intel.com> Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2021-03-05 17:03:35 +08:00
vtd: vtd@fed91000 {
compatible = "intel,vt-d";
reg = <0xfed91000 0x1000>;
status = "okay";
};
drivers: i2c_dw: User proper PCIe DT hierarchy Move all PCIe-based DT nodes under a PCIe bus and take advantage of the DT_ANY_INST_ON_BUS_STATUS_OKAY() and DT_INST_ON_BUS() macros. Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2021-01-19 18:46:43 +08:00
uart1_fixed: uart@fe040000 {
compatible = "ns16550";
reg = <0xfe040000 0x1000>;
reg-shift = <0>;
clock-frequency = <1843200>;
interrupts = <3 IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
interrupt-parent = <&intc>;
status = "disabled";
current-speed = <115200>;
};
uart2_fixed: uart@fe042000 {
compatible = "ns16550";
reg = <0xfe042000 0x1000>;
reg-shift = <0>;
clock-frequency = <1843200>;
interrupts = <4 IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
interrupt-parent = <&intc>;
status = "disabled";
current-speed = <115200>;
};
soc: x86: Add Elkhart Lake SoC definition Add a basic definition for the Intel Elkhart Lake SoC. Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2020-12-11 02:08:37 +08:00
drivers: gpio: Add GPIO driver for Intel Elkhart Lake Added support for GPIO driver for Intel Elkhart Lake board. The GPIO driver will support pin value read/write operations, pin direction and interrupt configuration. ACPI enumeration support and support for different GPIO communities is also present. Verified on ehl_crb. Signed-off-by: U Divya <u.divya@intel.com>
2021-05-06 08:41:30 +08:00
gpio_0_b: gpio@fd6e0700 {
compatible = "intel,gpio";
reg = <0xfd6e0700 0x1000>;
interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
interrupt-parent = <&intc>;
group-index = <0x0>;
gpio-controller;
#gpio-cells = <2>;
ngpios = <24>;
pin-offset = <0>;
status = "okay";
};
gpio_0_t: gpio@fd6e08a0 {
compatible = "intel,gpio";
reg = <0xfd6e08a0 0x1000>;
interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
interrupt-parent = <&intc>;
group-index = <0x1>;
gpio-controller;
#gpio-cells = <2>;
ngpios = <16>;
pin-offset = <26>;
status = "okay";
};
gpio_0_g: gpio@fd6e09a0 {
compatible = "intel,gpio";
reg = <0xfd6e09a0 0x1000>;
interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
interrupt-parent = <&intc>;
group-index = <0x2>;
gpio-controller;
#gpio-cells = <2>;
ngpios = <24>;
pin-offset = <42>;
status = "okay";
};
gpio_1_v: gpio@fd6d0700 {
compatible = "intel,gpio";
reg = <0xfd6d0700 0x1000>;
interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
interrupt-parent = <&intc>;
group-index = <0x0>;
gpio-controller;
#gpio-cells = <2>;
ngpios = <16>;
pin-offset = <0>;
status = "okay";
};
gpio_1_h: gpio@fd6d0800 {
compatible = "intel,gpio";
reg = <0xfd6d0800 0x1000>;
interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
interrupt-parent = <&intc>;
group-index = <0x1>;
gpio-controller;
#gpio-cells = <2>;
ngpios = <24>;
pin-offset = <16>;
status = "okay";
};
gpio_1_d: gpio@fd6d0980 {
compatible = "intel,gpio";
reg = <0xfd6d0980 0x1000>;
interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
interrupt-parent = <&intc>;
group-index = <0x2>;
gpio-controller;
#gpio-cells = <2>;
ngpios = <20>;
pin-offset = <40>;
status = "okay";
};
gpio_1_u: gpio@fd6d0ad0 {
compatible = "intel,gpio";
reg = <0xfd6d0ad0 0x1000>;
interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
interrupt-parent = <&intc>;
group-index = <0x3>;
gpio-controller;
#gpio-cells = <2>;
ngpios = <20>;
pin-offset = <61>;
status = "okay";
};
gpio_1_vG: gpio@fd6d0c50 {
compatible = "intel,gpio";
reg = <0xfd6d0c50 0x1000>;
interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
interrupt-parent = <&intc>;
group-index = <0x4>;
gpio-controller;
#gpio-cells = <2>;
ngpios = <28>;
pin-offset = <85>;
status = "okay";
};
gpio_3_s: gpio@fd6b0810 {
compatible = "intel,gpio";
reg = <0xfd6b0810 0x1000>;
interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
interrupt-parent = <&intc>;
group-index = <0x1>;
gpio-controller;
#gpio-cells = <2>;
ngpios = <2>;
pin-offset = <17>;
status = "okay";
};
gpio_3_a: gpio@fd6b0830 {
compatible = "intel,gpio";
reg = <0xfd6b0830 0x1000>;
interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
interrupt-parent = <&intc>;
group-index = <0x2>;
gpio-controller;
#gpio-cells = <2>;
ngpios = <24>;
pin-offset = <25>;
status = "okay";
};
gpio_3_vG: gpio@fd6b09b0 {
compatible = "intel,gpio";
reg = <0xfd6b09b0 0x1000>;
interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
interrupt-parent = <&intc>;
group-index = <0x3>;
gpio-controller;
#gpio-cells = <2>;
ngpios = <4>;
pin-offset = <49>;
status = "okay";
};
gpio_4_c: gpio@fd6a0700 {
compatible = "intel,gpio";
reg = <0xfd6a0700 0x1000>;
interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
interrupt-parent = <&intc>;
group-index = <0x0>;
gpio-controller;
#gpio-cells = <2>;
ngpios = <24>;
pin-offset = <0>;
status = "okay";
};
gpio_4_f: gpio@fd6a0880 {
compatible = "intel,gpio";
reg = <0xfd6a0880 0x1000>;
interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
interrupt-parent = <&intc>;
group-index = <0x1>;
gpio-controller;
#gpio-cells = <2>;
ngpios = <24>;
pin-offset = <24>;
status = "okay";
};
gpio_4_e: gpio@fd6a0a70 {
compatible = "intel,gpio";
reg = <0xfd6a0a70 0x1000>;
interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
interrupt-parent = <&intc>;
group-index = <0x3>;
gpio-controller;
#gpio-cells = <2>;
ngpios = <24>;
pin-offset = <57>;
status = "okay";
};
gpio_5_r: gpio@fd690700 {
compatible = "intel,gpio";
reg = <0xfd690700 0x1000>;
interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
interrupt-parent = <&intc>;
group-index = <0x0>;
gpio-controller;
#gpio-cells = <2>;
ngpios = <8>;
pin-offset = <0>;
status = "okay";
};
soc: x86: Add Elkhart Lake SoC definition Add a basic definition for the Intel Elkhart Lake SoC. Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2020-12-11 02:08:37 +08:00
hpet: hpet@fed00000 {
compatible = "intel,hpet";
reg = <0xfed00000 0x400>;
interrupts = <2 IRQ_TYPE_FIXED_EDGE_RISING 4>;
interrupt-parent = <&intc>;
status = "okay";
};
dts: x86: add CMOS RTC node to common devicetree files This adds the CMOS RTC node to the common devicetree files for x86. Note that this is not added to Lakemont, as it is usually used for embedded applications which would not have CMOS RTC. Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2022-02-15 05:31:58 +08:00
boards: ehl_crb: Add watchdog support Add watchdog support to ELkhart Lake board basically copying configuration from Raptor Lake. Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
2023-07-28 22:39:56 +08:00
tco_wdt: tco_wdt@400 {
compatible = "intel,tco-wdt";
reg = <0x0400 0x20>;
status = "disabled";
};
drivers: rtc: rtc_mc146818: Added RTC driver for Motorola MC146818B Added RTC driver that supports Motorola MC146818B Enabled RTC set/get time and alarm, alarm callback and update callback. Counter and RTC uses same hardware in case of Motorola MC146818, so they can't be used at a time. Updated stand-alone mc146818 counter dts instances to support rtc and counter with same compatible string of "motorola,mc146818" on ia32, atom, apollo_lake, elhart_lake and raptor_lake platforms. Signed-off-by: Anisetti Avinash Krishna <anisetti.avinash.krishna@intel.com>
2023-04-20 20:16:31 +08:00
rtc: counter: rtc@70 {
dts: x86: add CMOS RTC node to common devicetree files This adds the CMOS RTC node to the common devicetree files for x86. Note that this is not added to Lakemont, as it is usually used for embedded applications which would not have CMOS RTC. Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2022-02-15 05:31:58 +08:00
compatible = "motorola,mc146818";
reg = <0x70 0x0D 0x71 0x0D>;
drivers: rtc: rtc_mc146818: Added RTC driver for Motorola MC146818B Added RTC driver that supports Motorola MC146818B Enabled RTC set/get time and alarm, alarm callback and update callback. Counter and RTC uses same hardware in case of Motorola MC146818, so they can't be used at a time. Updated stand-alone mc146818 counter dts instances to support rtc and counter with same compatible string of "motorola,mc146818" on ia32, atom, apollo_lake, elhart_lake and raptor_lake platforms. Signed-off-by: Anisetti Avinash Krishna <anisetti.avinash.krishna@intel.com>
2023-04-20 20:16:31 +08:00
interrupts = <8 IRQ_TYPE_LOWEST_EDGE_RISING 3>;
interrupt-parent = <&intc>;
alarms-count = <1>;
dts: x86: add CMOS RTC node to common devicetree files This adds the CMOS RTC node to the common devicetree files for x86. Note that this is not added to Lakemont, as it is usually used for embedded applications which would not have CMOS RTC. Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2022-02-15 05:31:58 +08:00
status = "okay";
};
drivers: rtc: rtc_mc146818: Added RTC driver for Motorola MC146818B Added RTC driver that supports Motorola MC146818B Enabled RTC set/get time and alarm, alarm callback and update callback. Counter and RTC uses same hardware in case of Motorola MC146818, so they can't be used at a time. Updated stand-alone mc146818 counter dts instances to support rtc and counter with same compatible string of "motorola,mc146818" on ia32, atom, apollo_lake, elhart_lake and raptor_lake platforms. Signed-off-by: Anisetti Avinash Krishna <anisetti.avinash.krishna@intel.com>
2023-04-20 20:16:31 +08:00
soc: x86: Add Elkhart Lake SoC definition Add a basic definition for the Intel Elkhart Lake SoC. Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2020-12-11 02:08:37 +08:00
};
};