2018-02-12 16:17:50 +08:00
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/*
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* Copyright (c) 2018 Intel Corporation.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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2018-09-26 11:06:34 +08:00
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#include <mem.h>
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#include <st/f0/stm32f030.dtsi>
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2018-02-12 16:17:50 +08:00
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/ {
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2020-04-22 10:11:43 +08:00
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sram0: memory@20000000 {
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reg = <0x20000000 DT_SIZE_K(32)>;
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};
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2018-02-12 16:17:50 +08:00
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soc {
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2020-04-22 10:11:43 +08:00
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flash-controller@40022000 {
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flash0: flash@8000000 {
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reg = <0x08000000 DT_SIZE_K(256)>;
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};
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};
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2018-02-12 16:17:50 +08:00
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spi2: spi@40003800 {
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drivers/spi: stm32: Modify use of "st,stm32-spi-fifo" compatible
On stm32 spi devices, there are 2 main IP variants, with and w/o
fifo. Fifo is not really used today, but still there is some
additional code handling fifo. Today this code is protected under
Kconfig symbol SPI_STM32_HAS_FIFO.
This code carries redundant information vs dedicated compatible
"st,stm32-spi-fifo", which is provided as unique driver compatible
for devices supporting this IP as opposed to use of "st,stm32-spi"
when fifo is not supported.
Having these 2 compatibles defined exclusively is not convenient for
migration to DT_INST as DT_INST macros contain compatible string and
hence it cannot be used to provide common compatible code for devices
defining different compatibles.
Based on these observations, review stm32 spi devices compatible
declarations. Devices supporting fifo will now declare both
compatibles, as proposed by dt spec: "[compatible] property value
consists of a concatenated list of null terminated strings,
from most specific to most general". Hence field will now be:
"st,stm32-spi-fifo", "st,stm32-spi"
This way, fifo enabled stm32 spi devices will generate both:
DT_INST_STM32_SPI_FOO and DT_INST_STM32_SPI_FIFO_FOO
As well as:
DT_COMPAT_ST_STM32_SPI and DT_COMPAT_ST_STM32_SPI_FIFO
So, DT_INST_STM32_SPI_FOO could be used for device initialization.
Also DT_COMPAT_ST_STM32_SPI_FIFO could be used for FIFO handling
code inside driver. Hence use it to replace Kconfig symbol
SPI_STM32_HAS_FIFO.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2020-03-09 17:43:41 +08:00
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compatible = "st,stm32-spi-fifo", "st,stm32-spi";
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2018-02-12 16:17:50 +08:00
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40003800 0x400>;
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2018-06-22 19:54:24 +08:00
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00004000>;
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2018-02-12 16:17:50 +08:00
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interrupts = <26 3>;
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status = "disabled";
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label = "SPI_2";
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};
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2020-08-30 10:17:21 +08:00
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/*
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* USARTs 3-6 share the same IRQ on stm32f030Xc devices. This
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* configuration is not currently supported, so at most one of
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* these may be enabled at a time. Enabling more than one will
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* result in a build failure.
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*/
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usart3: serial@40004800 {
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compatible = "st,stm32-usart", "st,stm32-uart";
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reg = <0x40004800 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00040000>;
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interrupts = <29 0>;
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status = "disabled";
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label = "UART_3";
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};
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usart4: serial@40004c00 {
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compatible = "st,stm32-usart", "st,stm32-uart";
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reg = <0x40004c00 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00080000>;
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interrupts = <29 0>;
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status = "disabled";
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label = "UART_4";
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};
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usart5: serial@40005000 {
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compatible = "st,stm32-usart", "st,stm32-uart";
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reg = <0x40005000 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00100000>;
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interrupts = <29 0>;
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status = "disabled";
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label = "UART_5";
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};
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usart6: serial@40011400 {
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compatible = "st,stm32-usart", "st,stm32-uart";
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reg = <0x40011400 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00000020>;
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interrupts = <29 0>;
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status = "disabled";
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label = "UART_6";
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};
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2018-02-12 16:17:50 +08:00
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};
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};
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