Rico Ganahl 925303ede6 dts: stm32mp1: SPI2 mixup with SAI2, SPI3 mixup with SAI3 ... Device Tree address mixup between SAI2 <-> SPI2 and SAI3 <-> SPI3 Add functionality to SPI2/3 Tested on SPI2 Signed-off-by: Rico Ganahl <rico.ganahl@bytesatwork.ch>		2021-05-18 11:19:30 -05:00
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f0	dts/arm: st: Add clocks nodes for F0/F3/G0/G4	2021-04-29 16:41:26 +02:00
f1	dts/arm/st: f1: Use stm32f100 specific binding for pll	2021-05-04 13:02:26 -05:00
f2	dts: arm: stm32f{2,4,7}: fix device tree warning	2021-05-17 09:52:27 -05:00
f3	dts/arm: st: Add clocks nodes for F0/F3/G0/G4	2021-04-29 16:41:26 +02:00
f4	dts: arm: stm32f{2,4,7}: fix device tree warning	2021-05-17 09:52:27 -05:00
f7	dts: arm: stm32f{2,4,7}: fix device tree warning	2021-05-17 09:52:27 -05:00
g0	dts/arm: st: Add clocks nodes for F0/F3/G0/G4	2021-04-29 16:41:26 +02:00
g4	dts: arm: stm32g4: add can bindings to stm32g4 SoCs	2021-05-07 12:36:10 -05:00
h7	dts/arm/st: h7: Fix pll2 reg address	2021-05-04 13:57:41 -05:00
l0	dts/arm: stm32: Add clocks nodes on L0 and L1	2021-04-29 16:41:26 +02:00
l1	dts: arm: stm32l1 has a fixed lsi clock of 37kHz	2021-05-05 08:42:21 -04:00
l4	dts: arm: st: l4: add SPI2 node for stm32l412	2021-04-29 09:51:39 -04:00
l5	dts/arm/st: l5: Add clocks node to stm32l5.dtsi	2021-04-29 16:41:26 +02:00
mp1	dts: stm32mp1: SPI2 mixup with SAI2, SPI3 mixup with SAI3	2021-05-18 11:19:30 -05:00
wb	dts/arm: stm32: Add clocks nodes on stm32wb,l4 and stm32f4 series	2021-04-27 11:53:37 +02:00
wl	dts/arm: st: Add clocks node on stm32wl series	2021-04-29 16:41:26 +02:00