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zephyr/soc/neorv32/reset.S

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soc: riscv: privilege: add neorv32 processor suppport Add support for the open-source NEORV32 RISC-V compatible processor system (SoC). Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
2021-08-15 05:52:35 +08:00
/*
* Copyright (c) 2021 Henrik Brix Andersen <henrik@brixandersen.dk>
*
* SPDX-License-Identifier: Apache-2.0
*/
asm: update files with <zephyr/...> include prefix Assembler files were not migrated with the new <zephyr/...> prefix. Note that the conversion has been scripted, refer to #45388 for more details. Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-05-09 19:56:13 +08:00
#include <zephyr/toolchain.h>
soc: riscv: privilege: add neorv32 processor suppport Add support for the open-source NEORV32 RISC-V compatible processor system (SoC). Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
2021-08-15 05:52:35 +08:00
/* exports */
GTEXT(__reset)
/* imports */
GTEXT(__initialize)
SECTION_FUNC(reset, __reset)
/* Zerorize zero register */
lui x0, 0
soc: neorv32: Fix spelling in reset.S Fixes minor misspelling of instruction in the neorv32 reset.S. Signed-off-by: Daniel Mangum <georgedanielmangum@gmail.com>
2023-07-09 07:17:41 +08:00
/* Disable interrupts */
soc: riscv: privilege: add neorv32 processor suppport Add support for the open-source NEORV32 RISC-V compatible processor system (SoC). Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
2021-08-15 05:52:35 +08:00
csrw mstatus, x0
csrw mie, x0
#ifdef CONFIG_USERSPACE
/* Disable counter access outside M-mode */
csrw mcounteren, x0
#endif /* CONFIG_USERSPACE */
/* Allow mcycle and minstret counters to increment */
boards: riscv: neorv32: Updates compatibility to neoverse v1.8.6 With NEORV32 v1.8.2 the UART module was changed to a simpler implementation. This updates the UART driver for the open-source NEORV32 RISC-V compatible processor system (SOC). Signed-off-by: Tim-Marek Thomas <thomas@sra.uni-hannover.de>
2023-07-11 19:39:33 +08:00
li x11, ~2
soc: riscv: privilege: add neorv32 processor suppport Add support for the open-source NEORV32 RISC-V compatible processor system (SoC). Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
2021-08-15 05:52:35 +08:00
csrw mcountinhibit, x11
/* Zerorize counters */
csrw mcycle, x0
csrw mcycleh, x0
csrw minstret, x0
csrw minstreth, x0
/*
* Simplify dummy machine trap code by not having to decode
* instruction width.
*/
.option push
.option norvc
/*
* Temporarily setup a dummy machine trap vector to catch (and ignore)
* Store Access faults due to unimplemented peripherals.
*/
csrr x6, mtvec
la x7, __dummy_trap_handler
csrw mtvec, x7
/* Attempt to zerorize all IO peripheral registers */
la x8, __io_start
la x9, __io_end
1: sw x0, 0(x8)
addi x8, x8, 4
bne x8, x9, 1b
/* Restore previous machine trap vector */
csrw mtvec, x6
.option pop
/* Jump to __initialize */
call __initialize
.balign 4
SECTION_FUNC(reset, __dummy_trap_handler)
csrr x5, mepc
addi x5, x5, 4
csrw mepc, x5
mret