74 lines
1.3 KiB
ArmAsm
74 lines
1.3 KiB
ArmAsm
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/*
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* Copyright (c) 2021 Henrik Brix Andersen <henrik@brixandersen.dk>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <toolchain.h>
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/* exports */
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GTEXT(__reset)
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/* imports */
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GTEXT(__initialize)
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SECTION_FUNC(reset, __reset)
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/* Zerorize zero register */
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lui x0, 0
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/* Disable insterrupts */
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csrw mstatus, x0
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csrw mie, x0
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#ifdef CONFIG_USERSPACE
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/* Disable counter access outside M-mode */
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csrw mcounteren, x0
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#endif /* CONFIG_USERSPACE */
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/* Allow mcycle and minstret counters to increment */
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li x11, ~5
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csrw mcountinhibit, x11
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/* Zerorize counters */
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csrw mcycle, x0
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csrw mcycleh, x0
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csrw minstret, x0
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csrw minstreth, x0
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/*
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* Simplify dummy machine trap code by not having to decode
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* instruction width.
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*/
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.option push
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.option norvc
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/*
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* Temporarily setup a dummy machine trap vector to catch (and ignore)
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* Store Access faults due to unimplemented peripherals.
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*/
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csrr x6, mtvec
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la x7, __dummy_trap_handler
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csrw mtvec, x7
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/* Attempt to zerorize all IO peripheral registers */
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la x8, __io_start
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la x9, __io_end
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1: sw x0, 0(x8)
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addi x8, x8, 4
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bne x8, x9, 1b
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/* Restore previous machine trap vector */
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csrw mtvec, x6
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.option pop
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/* Jump to __initialize */
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call __initialize
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.balign 4
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SECTION_FUNC(reset, __dummy_trap_handler)
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csrr x5, mepc
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addi x5, x5, 4
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csrw mepc, x5
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mret
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