2021-08-10 17:22:31 +08:00
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/*
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* Copyright (c) 2021 Nordic Semiconductor ASA
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <drivers/pinctrl.h>
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#include <hal/nrf_gpio.h>
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BUILD_ASSERT(((NRF_PULL_NONE == NRF_GPIO_PIN_NOPULL) &&
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(NRF_PULL_DOWN == NRF_GPIO_PIN_PULLDOWN) &&
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(NRF_PULL_UP == NRF_GPIO_PIN_PULLUP)),
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"nRF pinctrl pull settings do not match HAL values");
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BUILD_ASSERT(((NRF_DRIVE_S0S1 == NRF_GPIO_PIN_S0S1) &&
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(NRF_DRIVE_H0S1 == NRF_GPIO_PIN_H0S1) &&
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(NRF_DRIVE_S0H1 == NRF_GPIO_PIN_S0H1) &&
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(NRF_DRIVE_H0H1 == NRF_GPIO_PIN_H0H1) &&
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(NRF_DRIVE_D0S1 == NRF_GPIO_PIN_D0S1) &&
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(NRF_DRIVE_D0H1 == NRF_GPIO_PIN_D0H1) &&
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(NRF_DRIVE_S0D1 == NRF_GPIO_PIN_S0D1) &&
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(NRF_DRIVE_H0D1 == NRF_GPIO_PIN_H0D1) &&
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#if defined(GPIO_PIN_CNF_DRIVE_E0E1)
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(NRF_DRIVE_E0E1 == NRF_GPIO_PIN_E0E1) &&
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#endif /* defined(GPIO_PIN_CNF_DRIVE_E0E1) */
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(1U)),
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"nRF pinctrl drive settings do not match HAL values");
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2021-08-10 17:24:54 +08:00
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#if DT_HAS_COMPAT_STATUS_OKAY(nordic_nrf_uart)
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#define NRF_PSEL_UART(reg, line) ((NRF_UART_Type *)reg)->PSEL##line
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#elif DT_HAS_COMPAT_STATUS_OKAY(nordic_nrf_uarte)
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#define NRF_PSEL_UART(reg, line) ((NRF_UARTE_Type *)reg)->PSEL.line
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#endif
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2021-08-10 17:22:31 +08:00
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/**
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* @brief Configure pin settings.
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*
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* @param pin Pin configuration.
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* @param dir Pin direction.
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* @param input Pin input buffer connection.
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*/
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__unused static void nrf_pin_configure(pinctrl_soc_pin_t pin,
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nrf_gpio_pin_dir_t dir,
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nrf_gpio_pin_input_t input)
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{
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/* force input direction and disconnected buffer for low power */
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if (NRF_GET_LP(pin) == NRF_LP_ENABLE) {
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dir = NRF_GPIO_PIN_DIR_INPUT;
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input = NRF_GPIO_PIN_INPUT_DISCONNECT;
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}
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nrf_gpio_cfg(NRF_GET_PIN(pin), dir, input, NRF_GET_PULL(pin),
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NRF_GET_DRIVE(pin), NRF_GPIO_PIN_NOSENSE);
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}
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int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt,
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uintptr_t reg)
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{
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for (uint8_t i = 0U; i < pin_cnt; i++) {
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switch (NRF_GET_FUN(pins[i])) {
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2021-08-10 17:24:54 +08:00
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#if defined(NRF_PSEL_UART)
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case NRF_FUN_UART_TX:
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NRF_PSEL_UART(reg, TXD) = NRF_GET_PIN(pins[i]);
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nrf_gpio_pin_write(NRF_GET_PIN(pins[i]), 1);
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nrf_pin_configure(pins[i], NRF_GPIO_PIN_DIR_OUTPUT,
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NRF_GPIO_PIN_INPUT_DISCONNECT);
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break;
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case NRF_FUN_UART_RX:
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NRF_PSEL_UART(reg, RXD) = NRF_GET_PIN(pins[i]);
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nrf_pin_configure(pins[i], NRF_GPIO_PIN_DIR_INPUT,
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NRF_GPIO_PIN_INPUT_CONNECT);
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break;
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case NRF_FUN_UART_RTS:
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NRF_PSEL_UART(reg, RTS) = NRF_GET_PIN(pins[i]);
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nrf_gpio_pin_write(NRF_GET_PIN(pins[i]), 1);
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nrf_pin_configure(pins[i], NRF_GPIO_PIN_DIR_OUTPUT,
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NRF_GPIO_PIN_INPUT_DISCONNECT);
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break;
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case NRF_FUN_UART_CTS:
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NRF_PSEL_UART(reg, CTS) = NRF_GET_PIN(pins[i]);
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nrf_pin_configure(pins[i], NRF_GPIO_PIN_DIR_INPUT,
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NRF_GPIO_PIN_INPUT_CONNECT);
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break;
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#endif /* defined(NRF_PSEL_UART) */
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2021-08-10 17:22:31 +08:00
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default:
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return -ENOTSUP;
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}
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}
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return 0;
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}
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