zephyr/drivers/spi/Kconfig.dw

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# Kconfig.dw - DesignWare SPI driver configuration options
#
#
# Copyright (c) 2015-2016 Intel Corporation
#
# SPDX-License-Identifier: Apache-2.0
#
config HAS_SPI_DW
bool
help
Signifies whether DesignWare SPI compatible HW is available
menuconfig SPI_DW
bool "Designware SPI controller driver"
depends on HAS_SPI_DW
help
Enable support for Designware's SPI controllers.
if SPI_DW
config SPI_DW_ARC_AUX_REGS
bool "Registers are part of ARC auxiliary registers"
depends on SPI_DW && ARC
default y
help
SPI IP block registers are part of user extended auxiliary
registers and thus their access is different than memory
mapped registers.
config SPI_DW_FIFO_DEPTH
int "RX and TX FIFO Depth"
help
Corresponds to the SSI_TX_FIFO_DEPTH and
SSI_RX_FIFO_DEPTH of the DesignWare Synchronous
Serial Interface. Depth ranges from 2-256.
if SPI_0
config SPI_DW_PORT_0_INTERRUPT_SINGLE_LINE
bool "Single interrupt line for all interrupts"
default y
help
Only one line is used to trigger interrupts: RX, TX and ERROR
interrupt go all through that line, undifferentiated.
config SPI_DW_PORT_0_CLOCK_GATE
bool "Enable clock gating"
depends on CLOCK_CONTROL
if SPI_DW_PORT_0_CLOCK_GATE
config SPI_DW_PORT_0_CLOCK_GATE_DRV_NAME
string
config SPI_DW_PORT_0_CLOCK_GATE_SUBSYS
int "Clock controller's subsystem"
endif # SPI_DW_PORT_0_CLOCK_GATE
endif # SPI_0
if SPI_1
config SPI_DW_PORT_1_INTERRUPT_SINGLE_LINE
bool "Single interrupt line for all interrupts"
default y
config SPI_DW_PORT_1_CLOCK_GATE
bool "Enable clock gating"
depends on CLOCK_CONTROL
if SPI_DW_PORT_1_CLOCK_GATE
config SPI_DW_PORT_1_CLOCK_GATE_DRV_NAME
string
config SPI_DW_PORT_1_CLOCK_GATE_SUBSYS
int "Clock controller's subsystem"
endif # SPI_DW_PORT_1_CLOCK_GATE
endif # SPI_1
if SPI_2
config SPI_DW_PORT_2_INTERRUPT_SINGLE_LINE
bool "Single interrupt line for all interrupts"
default y
help
Only one line is used to trigger interrupts: RX, TX and ERROR
interrupt go all through that line, undifferentiated.
config SPI_DW_PORT_2_CLOCK_GATE
bool "Enable clock gating"
depends on CLOCK_CONTROL
if SPI_DW_PORT_2_CLOCK_GATE
config SPI_DW_PORT_2_CLOCK_GATE_DRV_NAME
string
default ""
config SPI_DW_PORT_2_CLOCK_GATE_SUBSYS
int "Clock controller's subsystem"
endif # SPI_DW_PORT_2_CLOCK_GATE
endif # SPI_2
if SPI_3
config SPI_DW_PORT_3_INTERRUPT_SINGLE_LINE
bool "Single interrupt line for all interrupts"
default y
help
Only one line is used to trigger interrupts: RX, TX and ERROR
interrupt go all through that line, undifferentiated.
config SPI_DW_PORT_3_CLOCK_GATE
bool "Enable clock gating"
depends on CLOCK_CONTROL
if SPI_DW_PORT_3_CLOCK_GATE
config SPI_DW_PORT_3_CLOCK_GATE_DRV_NAME
string
default ""
config SPI_DW_PORT_3_CLOCK_GATE_SUBSYS
int "Clock controller's subsystem"
endif # SPI_DW_PORT_3_CLOCK_GATE
endif # SPI_3
endif # SPI_DW