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zephyr/drivers/spi/Kconfig.dw

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spi: restructure kconfig options () Moves config options for each controllers into their own Kconfig files. This keeps upper level Kconfig from getting too big. () Options for each controller are moved under their own submenus. Origin: refactored from existing file Change-Id: I813694f26126b43523b08ebdb0a5383edd241cda Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2016-03-18 02:21:49 +08:00
# Kconfig.dw - DesignWare SPI driver configuration options
#
#
# Copyright (c) 2015-2016 Intel Corporation
#
license: Replace Apache boilerplate with SPDX tag Replace the existing Apache 2.0 boilerplate header with an SPDX tag throughout the zephyr code tree. This patch was generated via a script run over the master branch. Also updated doc/porting/application.rst that had a dependency on line numbers in a literal include. Manually updated subsys/logging/sys_log.c that had a malformed header in the original file. Also cleanup several cases that already had a SPDX tag and we either got a duplicate or missed updating. Jira: ZEP-1457 Change-Id: I6131a1d4ee0e58f5b938300c2d2fc77d2e69572c Signed-off-by: David B. Kinder <david.b.kinder@intel.com> Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2017-01-19 09:01:01 +08:00
# SPDX-License-Identifier: Apache-2.0
spi: restructure kconfig options () Moves config options for each controllers into their own Kconfig files. This keeps upper level Kconfig from getting too big. () Options for each controller are moved under their own submenus. Origin: refactored from existing file Change-Id: I813694f26126b43523b08ebdb0a5383edd241cda Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2016-03-18 02:21:49 +08:00
#
menuconfig SPI_DW
bool
prompt "Designware SPI controller driver"
depends on SPI
default n
help
Enable support for Designware's SPI controllers.
if SPI_DW
config SPI_DW_ARC_AUX_REGS
bool "Registers are part of ARC auxiliary registers"
depends on SPI_DW && ARC
default y
help
SPI IP block registers are part of user extended auxiliary
registers and thus their access is different than memory
mapped registers.
choice
depends on SPI_DW
prompt "DesignWare SPI interrupt management logic"
default SPI_DW_INTERRUPT_SINGLE_LINE
config SPI_DW_INTERRUPT_SINGLE_LINE
bool "Single interrupt line for all interrupts"
help
Only one line is used to trigger interrupts: RX, TX and ERROR
interrupt go all through that line, undifferentiated.
config SPI_DW_INTERRUPT_SEPARATED_LINES
bool "One line per-interrupt type (RX, TX and ERROR)"
help
Each interrupt gets a dedicated line
endchoice
Cleanup whitespace in Kconfig files Convert leading whitespace into tabs in Kconfig files. Also replaced double spaces between config and <prompt>. Change-Id: I341c718ecf4143529b477c239bbde88e18f37062 Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2016-05-25 07:17:13 +08:00
config SPI_DW_CLOCK_GATE
spi: restructure kconfig options () Moves config options for each controllers into their own Kconfig files. This keeps upper level Kconfig from getting too big. () Options for each controller are moved under their own submenus. Origin: refactored from existing file Change-Id: I813694f26126b43523b08ebdb0a5383edd241cda Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2016-03-18 02:21:49 +08:00
bool "Enable glock gating"
boards: rename Quark SE Devboard to Quark SE C1000 This board now has an official name and will be available soon: http://www.intel.com/content/www/us/en/embedded/products/quark/mcu/se-soc/overview.html Jira: ZEP-758 Change-Id: Ia16d33722308cf81471321c3063bdc75055a4d50 Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-08-30 20:41:04 +08:00
depends on SPI_DW && SOC_QUARK_SE_C1000
spi: restructure kconfig options () Moves config options for each controllers into their own Kconfig files. This keeps upper level Kconfig from getting too big. () Options for each controller are moved under their own submenus. Origin: refactored from existing file Change-Id: I813694f26126b43523b08ebdb0a5383edd241cda Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2016-03-18 02:21:49 +08:00
select CLOCK_CONTROL
default n
config SPI_DW_CLOCK_GATE_DRV_NAME
string
depends on SPI_DW_CLOCK_GATE
default ""
spi: For spi_dw, added SPI_DW_FIFO_DEPTH as configurable paramter When using the Synopsys DesignWare Synchronous Serial Interface (SSI), the FIFO depth can vary from 2-256, depending upon how this module is built. For quark_se_ss, it was using a depth of 8. For EM Starterkit, it will be 32. Adding this now as a configurable option. A larger FIFO really helps reduce SPI interrupts. Change-Id: Id2bc8470bfc08ab447d38b89c7904cff010c63bd Signed-off-by: Chuck Jordan <cjordan@synopsys.com>
2016-05-19 04:11:35 +08:00
config SPI_DW_FIFO_DEPTH
spell: Kconfig help typos: /arch Fix misspellings in Kconfig help text and made spelling of RX and TX consistent (from reviewer comments) Change-Id: Ie9d4c3863cd210e7a17b50a85a7e64156b6bf3d7 Signed-off-by: David B. Kinder <david.b.kinder@intel.com>
2017-04-25 02:30:10 +08:00
int "RX and TX FIFO Depth"
spi: For spi_dw, added SPI_DW_FIFO_DEPTH as configurable paramter When using the Synopsys DesignWare Synchronous Serial Interface (SSI), the FIFO depth can vary from 2-256, depending upon how this module is built. For quark_se_ss, it was using a depth of 8. For EM Starterkit, it will be 32. Adding this now as a configurable option. A larger FIFO really helps reduce SPI interrupts. Change-Id: Id2bc8470bfc08ab447d38b89c7904cff010c63bd Signed-off-by: Chuck Jordan <cjordan@synopsys.com>
2016-05-19 04:11:35 +08:00
help
Corresponds to the SSI_TX_FIFO_DEPTH and
spell: fix Kconfig help typos: /boards /drivers Fix misspellings in Kconfig help text Change-Id: I3ae28a5d23d8e266612114bc0eb8a6e158129dc7 Signed-off-by: David B. Kinder <david.b.kinder@intel.com>
2017-04-22 01:29:51 +08:00
SSI_RX_FIFO_DEPTH of the DesignWare Synchronous
spi: For spi_dw, added SPI_DW_FIFO_DEPTH as configurable paramter When using the Synopsys DesignWare Synchronous Serial Interface (SSI), the FIFO depth can vary from 2-256, depending upon how this module is built. For quark_se_ss, it was using a depth of 8. For EM Starterkit, it will be 32. Adding this now as a configurable option. A larger FIFO really helps reduce SPI interrupts. Change-Id: Id2bc8470bfc08ab447d38b89c7904cff010c63bd Signed-off-by: Chuck Jordan <cjordan@synopsys.com>
2016-05-19 04:11:35 +08:00
Serial Interface. Depth ranges from 2-256.
spi: restructure kconfig options () Moves config options for each controllers into their own Kconfig files. This keeps upper level Kconfig from getting too big. () Options for each controller are moved under their own submenus. Origin: refactored from existing file Change-Id: I813694f26126b43523b08ebdb0a5383edd241cda Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2016-03-18 02:21:49 +08:00
Cleanup whitespace in Kconfig files Convert leading whitespace into tabs in Kconfig files. Also replaced double spaces between config and <prompt>. Change-Id: I341c718ecf4143529b477c239bbde88e18f37062 Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2016-05-25 07:17:13 +08:00
config SPI_DW_PORT_0_CLOCK_GATE_SUBSYS
spi: restructure kconfig options () Moves config options for each controllers into their own Kconfig files. This keeps upper level Kconfig from getting too big. () Options for each controller are moved under their own submenus. Origin: refactored from existing file Change-Id: I813694f26126b43523b08ebdb0a5383edd241cda Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2016-03-18 02:21:49 +08:00
int "Clock controller's subsystem"
depends on SPI_DW_CLOCK_GATE
Cleanup whitespace in Kconfig files Convert leading whitespace into tabs in Kconfig files. Also replaced double spaces between config and <prompt>. Change-Id: I341c718ecf4143529b477c239bbde88e18f37062 Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2016-05-25 07:17:13 +08:00
config SPI_DW_PORT_1_CLOCK_GATE_SUBSYS
spi: restructure kconfig options () Moves config options for each controllers into their own Kconfig files. This keeps upper level Kconfig from getting too big. () Options for each controller are moved under their own submenus. Origin: refactored from existing file Change-Id: I813694f26126b43523b08ebdb0a5383edd241cda Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2016-03-18 02:21:49 +08:00
int "Clock controller's subsystem"
depends on SPI_DW_CLOCK_GATE
endif # SPI_DW