zephyr/dts/arm/nxp/nxp_lpc54xxx.dtsi

/*
 * Copyright (c) 2017, NXP
 *
 * SPDX-License-Identifier: Apache-2.0
 */

#include <dt-bindings/gpio/gpio.h>

/ {
	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			compatible = "arm,cortex-m4f";
			reg = <0>;
		};

		cpu1: cpu@1 {
			compatible = "arm,cortex-m0+";
			reg = <1>;
		};
	};

	sram0:memory@20000000 {
		compatible = "mmio-sram";
		reg = <0x20000000 0x10000>;
	};

	sram1:memory@20010000 {
		compatible = "mmio-sram";
		reg = <0x20010000 0x10000>;
	};

	sram2:memory@20020000 {
		compatible = "mmio-sram";
		reg = <0x20020000 0x8000>;
	};

	sramx:memory@40000000{
		compatible = "mmio-sram";
		reg = <0x40000000 0x8000>;
	};

	soc {

		flash0:flash@0 {
			compatible = "soc-nv-flash";
			reg = <0 0x40000>;
		};

		usart0:usart@40086000 {
			compatible = "nxp,lpc-usart";
			reg = <0x40086000 0xE44>;
			interrupts = <14 0>;
			label = "USART_0";
			status = "disabled";
		};

		gpio0: gpio@0 {
			compatible = "nxp,lpc-gpio";
			reg = <0x4008c000 0x2488>;
			interrupts = <4 2>,<5 2>,<6 2>,<7 2>;
			label = "GPIO_0";
			gpio-controller;
			#gpio-cells = <2>;
		};

		gpio1: gpio@1 {
			compatible = "nxp,lpc-gpio";
			reg = <0x4008C000 0x2488>;
			interrupts = <32 2>,<33 2>,<34 2>,<35 2>;
			label = "GPIO_1";
			gpio-controller;
			#gpio-cells = <2>;
		};

		mailbox0:mailbox@4008b000 {
			compatible = "nxp,lpc-mailbox";
			reg = <0x4008b000 0xEC>;
			interrupts = <31 0>;
			label = "MAILBOX_0";
			status = "disabled";
		};

		spi5: spi@40096000 {
			compatible = "nxp,lpc-spi";
			reg = <0x40096000 0x1000>;
			interrupts = <19 0>;
			label = "SPI_5";
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
		};
	};
};

&nvic {
	arm,num-irq-priority-bits = <3>;
};