OrgZephyr/zephyr
OrgZephyr
/
zephyr
mirror of https://github.com/zephyrproject-rtos/zephyr.git
1
0
Fork 0
Code Issues Releases Wiki Activity
zephyr/arch/riscv/core/asm_macros.inc

88 lines
1.3 KiB
PHP
Raw Normal View History

riscv: better abstraction for register-wide load/store opcodes Those are prominent enough that having RV_OP_LOADREG and RV_OP_STOREREG shouting at you all over the place is rather unpleasant and bad taste. Let's create pseudo-instructions of our own with assembler macros rather than preprocessor defines and only in assembly scope. This makes the asm code way more uniform and readable. Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
2022-02-23 03:09:55 +08:00
/*
* Assembly macros and helpers
*
* Copyright (c) 2022 BayLibre, SAS
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifdef CONFIG_64BIT
/* register-wide load/store based on ld/sd (XLEN = 64) */
.macro lr, rd, mem
ld \rd, \mem
.endm
.macro sr, rs, mem
sd \rs, \mem
.endm
#else
/* register-wide load/store based on lw/sw (XLEN = 32) */
.macro lr, rd, mem
lw \rd, \mem
.endm
.macro sr, rs, mem
sw \rs, \mem
.endm
#endif
riscv: better abstraction for register-wide FP load/store opcodes Same rationale as preceding commit. Let's create pseudo-instructions in assembly scope to make the code more uniform and readable. Furthermore the definition of COPY_ESF_FP() was wrong as the width of floating point registers vary not according to CONFIG_64BIT but CONFIG_CPU_HAS_FPU_DOUBLE_PRECISION. It is therefore wrong to use lr/sr (previously RV_OP_LOADREG/RV_OP_STOREREG) and a regular temporary register to transfer such content. Note: There are far more efficient ways to copy FP context around but such optimisations will come separately. Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
2022-02-23 03:29:34 +08:00
#ifdef CONFIG_CPU_HAS_FPU_DOUBLE_PRECISION
.macro flr, rd, mem
fld \rd, \mem
.endm
.macro fsr, rs, mem
fsd \rs, \mem
.endm
#else
.macro flr, rd, mem
flw \rd, \mem
.endm
.macro fsr, rs, mem
fsw \rs, \mem
.endm
#endif
riscv: isr.S: compute _current_cpu using CPU number on SMP To do so efficiently on systems without the mul instruction, we use shifts and adds which is faster and sometimes smaller than a plain loop. Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
2022-03-10 12:47:38 +08:00
/*
* Perform rd += rs * mult using only shifts and adds.
* Useful when the mul instruction isn't available.
* mult must be a constant. rs will be clobbered.
*/
.macro shiftmul_add rd, rs, mult
beqz \rs, 999f
.set _bitpos, 0
.set _lastbitpos, 0
.rept 32
.if ((\mult) & (1 << _bitpos))
.if (_bitpos - _lastbitpos) != 0
slli \rs, \rs, (_bitpos - _lastbitpos)
.set _lastbitpos, _bitpos
.endif
add \rd, \rd, \rs
.endif
.set _bitpos, _bitpos + 1
.endr
999:
.endm
riscv: abstract RV32E register access ... and avoid macro duplication. Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
2022-06-16 06:41:36 +08:00
/* lowest common denominator for register availability */
#if defined(CONFIG_RISCV_ISA_RV32E)
#define RV_E(op...) op
#define RV_I(op...) /* unavailable */
#else
#define RV_E(op...) op
#define RV_I(op...) op
#endif