176713abfe
RISC-V Spec requires minimum alignment of trap handling code to be dependent from MTVEC.BASE field size. Minimum alignment for RISC-V platforms is 4 bytes, but maximum is platform or application-specific. Currently there is no common approach to align the trap handling code for RISC-V and some platforms use custom wrappers to align _isr_wrapper properly. This change introduces a generic solution, CONFIG_RISCV_TRAP_HANDLER_ALIGNMENT configuration option which sets the alignment of a RISC-V trap handling code. The existing custom solutions for some platforms remain operational, since the default alignment is set to minimal possible (4 bytes) and will be overloaded by potentially larger alignment of custom solutions. Signed-off-by: Alexander Razinkov <alexander.razinkov@syntacore.com> |
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| .. | ||
| offsets | ||
| CMakeLists.txt | ||
| asm_macros.inc | ||
| coredump.c | ||
| cpu_idle.c | ||
| fatal.c | ||
| fpu.S | ||
| fpu.c | ||
| irq_manage.c | ||
| irq_offload.c | ||
| isr.S | ||
| pmp.S | ||
| pmp.c | ||
| prep_c.c | ||
| reboot.c | ||
| reset.S | ||
| semihost.c | ||
| smp.c | ||
| switch.S | ||
| thread.c | ||
| tls.c | ||
| userspace.S | ||
| vector_table.ld | ||