60 lines
1.9 KiB
C
60 lines
1.9 KiB
C
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/*
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* Copyright (c) 2017 Intel Corporation
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef __INC_MEMORY_H
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#define __INC_MEMORY_H
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/* L2 HP SRAM */
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#define L2_VECTOR_SIZE 0x1000
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/* The reset vector address in SRAM and its size */
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#define XCHAL_RESET_VECTOR0_PADDR_SRAM L2_SRAM_BASE
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#define MEM_RESET_TEXT_SIZE 0x268
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#define MEM_RESET_LIT_SIZE 0x8
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/* This is the base address of all the vectors defined in SRAM */
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#define XCHAL_VECBASE_RESET_PADDR_SRAM (L2_SRAM_BASE + 0x400)
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#define MEM_VECBASE_LIT_SIZE 0x178
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/* The addresses of the vectors in SRAM.
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* Only the memerror vector continues to point to its ROM address.
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*/
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#define XCHAL_INTLEVEL2_VECTOR_PADDR_SRAM (L2_SRAM_BASE + 0x580)
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#define XCHAL_INTLEVEL3_VECTOR_PADDR_SRAM (L2_SRAM_BASE + 0x5C0)
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#define XCHAL_INTLEVEL4_VECTOR_PADDR_SRAM (L2_SRAM_BASE + 0x600)
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#define XCHAL_INTLEVEL5_VECTOR_PADDR_SRAM (L2_SRAM_BASE + 0x640)
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#define XCHAL_INTLEVEL6_VECTOR_PADDR_SRAM (L2_SRAM_BASE + 0x680)
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#define XCHAL_INTLEVEL7_VECTOR_PADDR_SRAM (L2_SRAM_BASE + 0x6C0)
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#define XCHAL_KERNEL_VECTOR_PADDR_SRAM (L2_SRAM_BASE + 0x700)
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#define XCHAL_USER_VECTOR_PADDR_SRAM (L2_SRAM_BASE + 0x740)
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#define XCHAL_DOUBLEEXC_VECTOR_PADDR_SRAM (L2_SRAM_BASE + 0x7C0)
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/* Vector and literal sizes */
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#define MEM_VECT_LIT_SIZE 0x8
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#define MEM_VECT_TEXT_SIZE 0x38
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#define MEM_VECT_SIZE (MEM_VECT_TEXT_SIZE +\
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MEM_VECT_LIT_SIZE)
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/* The memerror vector address is copied as is from core-isa.h */
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#define XCHAL_MEMERROR_VECTOR_PADDR 0xBEFE0400
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#define MEM_ERROR_TEXT_SIZE 0x180
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#define MEM_ERROR_LIT_SIZE 0x8
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/* text and data share the same L2 HP SRAM on Intel S1000 */
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#define TEXT_BASE (L2_SRAM_BASE + L2_VECTOR_SIZE)
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#define TEXT_SIZE 0x16000
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/* size of the Interrupt Descriptor Table (IDT) */
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#define IDT_SIZE 0x2000
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/* initialized data */
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#define DATA_SIZE 0x10000
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/* bss data */
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#define BSS_DATA_SIZE 0x8000
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#endif /* __INC_MEMORY_H */
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