zephyr/soc/xtensa
Sathish Kuttan 3d19f891a3 soc: intel_s1000: GNA model - linker script entry
Add a linker script entry for embedding a GNA model at a
4KB page aligned address in .data section

Signed-off-by: Sathish Kuttan <sathish.k.kuttan@intel.com>
2018-11-08 17:08:19 -05:00
..
D_108mini linker: warn about orphan sections 2018-10-19 16:11:34 -04:00
D_212GP linker: warn about orphan sections 2018-10-19 16:11:34 -04:00
D_233L linker: warn about orphan sections 2018-10-19 16:11:34 -04:00
XRC_D2PM_5swIrq linker: warn about orphan sections 2018-10-19 16:11:34 -04:00
XRC_FUSION_AON_ALL_LM linker: warn about orphan sections 2018-10-19 16:11:34 -04:00
esp32 soc: esp32: Update auto-generated _soc_inthandlers.h 2018-10-27 21:25:57 -04:00
hifi2_std linker: warn about orphan sections 2018-10-19 16:11:34 -04:00
hifi3_bd5 linker: warn about orphan sections 2018-10-19 16:11:34 -04:00
hifi3_bd5_call0 linker: warn about orphan sections 2018-10-19 16:11:34 -04:00
hifi4_bd7 linker: warn about orphan sections 2018-10-19 16:11:34 -04:00
hifi_mini linker: warn about orphan sections 2018-10-19 16:11:34 -04:00
hifi_mini_4swIrq linker: warn about orphan sections 2018-10-19 16:11:34 -04:00
intel_s1000 soc: intel_s1000: GNA model - linker script entry 2018-11-08 17:08:19 -05:00
sample_controller linker: warn about orphan sections 2018-10-19 16:11:34 -04:00