2016-10-28 18:02:20 +08:00
|
|
|
# Zephyr Kernel Configuration
|
|
|
|
|
CONFIG_ARM=y
|
|
|
|
|
CONFIG_ARCH="arm"
|
|
|
|
|
CONFIG_SOC="stm32f334x8"
|
|
|
|
|
CONFIG_SOC_SERIES="stm32f3"
|
|
|
|
|
CONFIG_SOC_FAMILY="st_stm32"
|
|
|
|
|
CONFIG_BOARD="nucleo_f334r8"
|
|
|
|
|
CONFIG_SOC_SERIES_STM32F3X=y
|
|
|
|
|
|
|
|
|
|
# Platform Configuration
|
|
|
|
|
CONFIG_SOC_FAMILY_STM32=y
|
|
|
|
|
CONFIG_SOC_STM32F334X8=y
|
|
|
|
|
CONFIG_BOARD_NUCLEO_F334R8=y
|
|
|
|
|
|
|
|
|
|
# General Kernel Options
|
|
|
|
|
CONFIG_CORTEX_M_SYSTICK=y
|
|
|
|
|
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=72000000
|
|
|
|
|
|
|
|
|
|
# Serial Drivers
|
|
|
|
|
CONFIG_SERIAL=y
|
|
|
|
|
CONFIG_SERIAL_HAS_DRIVER=y
|
|
|
|
|
CONFIG_UART_INTERRUPT_DRIVEN=y
|
|
|
|
|
CONFIG_UART_STM32=y
|
|
|
|
|
# enable USART2 - passthrough to STLINK v2 connector
|
|
|
|
|
CONFIG_UART_STM32_PORT_2=y
|
|
|
|
|
# enable console on this port by default
|
|
|
|
|
CONFIG_CONSOLE=y
|
|
|
|
|
CONFIG_UART_CONSOLE=y
|
|
|
|
|
|
|
|
|
|
# Pinmux Driver
|
|
|
|
|
CONFIG_PINMUX=y
|
|
|
|
|
CONFIG_PINMUX_STM32=y
|
|
|
|
|
|
|
|
|
|
# GPIO Controller
|
|
|
|
|
CONFIG_GPIO=y
|
|
|
|
|
CONFIG_GPIO_STM32=y
|
|
|
|
|
CONFIG_GPIO_STM32_PORTA=y
|
|
|
|
|
CONFIG_GPIO_STM32_PORTB=y
|
|
|
|
|
CONFIG_GPIO_STM32_PORTC=y
|
|
|
|
|
|
2017-01-24 18:44:03 +08:00
|
|
|
# Clock configuration
|
2016-10-28 18:02:20 +08:00
|
|
|
CONFIG_CLOCK_CONTROL=y
|
2017-01-24 18:44:03 +08:00
|
|
|
# SYSCLK selection
|
|
|
|
|
CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL=y
|
|
|
|
|
# HSE configuration
|
|
|
|
|
CONFIG_CLOCK_STM32_HSE_CLOCK=8000000
|
|
|
|
|
# PLL configuration
|
|
|
|
|
CONFIG_CLOCK_STM32_PLL_SRC_HSE=y
|
|
|
|
|
# produce 72MHz clock at PLL output
|
|
|
|
|
CONFIG_CLOCK_STM32_PLL_PREDIV=1
|
|
|
|
|
CONFIG_CLOCK_STM32_PLL_MULTIPLIER=9
|
|
|
|
|
CONFIG_CLOCK_STM32_AHB_PRESCALER=1
|
|
|
|
|
CONFIG_CLOCK_STM32_APB1_PRESCALER=2
|
|
|
|
|
CONFIG_CLOCK_STM32_APB2_PRESCALER=1
|
