71 lines
1.7 KiB
YAML
71 lines
1.7 KiB
YAML
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# Copyright (c) 2021, Linaro ltd
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# SPDX-License-Identifier: Apache-2.0
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description: |
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PLL node binding for STM32H7 devices
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It can be used to describe 3 different PLLs: PLL1 (Main PLL), PLL2 and PLL3.
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Only PLL1 and PLL3 are supported for now.
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These PLLs could take one of clk_hse, clk_hsi or clk_csi as input clock, with
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an input frequency from 1 to 16 MHz. PLLM factor is used to set the input
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clock in this acceptable range.
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Each PLL can have up to 3 output clocks and for each output clock, the
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frequency can be computed with the following formulae:
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f(PLL_Px) = f(VCOx clock) / PLLPx -> pllx_p_ck ((pll1_p_ck : sys_ck))
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f(PLL_Qx) = f(VCOx clock) / PLLQx -> pllx_q_ck
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f(PLL_Rx) = f(VCOx clock) / PLLRx -> pllx_r_ck
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with f(VCOx clock) = f(REFx_CK) × (PLLNx / PLLMx)
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The PLL output frequency must not exceed 80 MHz.
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compatible: "st,stm32h7-pll-clock"
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include: [clock-controller.yaml, base.yaml]
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properties:
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"#clock-cells":
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const: 0
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clocks:
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required: true
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div-m:
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type: int
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required: true
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description: |
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Division factor for PLLx
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input clock
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Valid range: 0 - 63
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mul-n:
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type: int
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required: true
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description: |
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Main PLL multiplication factor for VCOx
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Valid range: 4 - 512
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div-p:
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type: int
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required: false
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description: |
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PLL division factor for pllx_p_ck
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Valid range: 1 - 128
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div-q:
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type: int
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required: false
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description: |
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PLL division factor for pllx_q_ck
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Valid range: 1 - 128
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div-r:
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type: int
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required: false
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description: |
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PLL division factor for pllx_r_ck
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Valid range: 1 - 128
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