73 lines
1.6 KiB
Plaintext
73 lines
1.6 KiB
Plaintext
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# Copyright 2023 The ChromiumOS Authors
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# SPDX-License-Identifier: Apache-2.0
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orsource "*/Kconfig.defconfig"
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if SOC_FAMILY_MTK_ADSP
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config INTC_MTK_ADSP
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default y
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config XTENSA_SMALL_VECTOR_TABLE_ENTRY
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default y
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config XTENSA_USE_CORE_CRT1
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default n
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config MULTI_LEVEL_INTERRUPTS
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default y
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config 2ND_LEVEL_INTERRUPTS
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default y
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config MAX_IRQ_PER_AGGREGATOR
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default 32
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config 2ND_LVL_ISR_TBL_OFFSET
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default 32
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config MTK_ADSP_TIMER
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default y
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config XTENSA_TIMER
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default n
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config MAIN_STACK_SIZE
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default 2048
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# This platform has a single big DRAM region where most linkage
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# happens. The libc heap normally wants to steal all of it, when in
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# fact SOF has its own heap. Just leave a little for stray malloc()
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# calls to find.
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config COMMON_LIBC_MALLOC_ARENA_SIZE
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default 32768
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# Don't build the HAL if the toolchain already includes it. Note that
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# this is done in the SOC layer historically, really this belongs in
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# arch/xtensa or the toolchain integration.
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#
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config XTENSA_HAL
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default n if "$(ZEPHYR_TOOLCHAIN_VARIANT)" = "xcc"
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default n if "$(ZEPHYR_TOOLCHAIN_VARIANT)" = "xt-clang"
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default y
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config SOC_TOOLCHAIN_NAME
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default "mtk_mt8195_adsp"
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config XTENSA_RESET_VECTOR
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default n
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# This single-core device doesn't have S32C1I and so has no built-in
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# atomics. Note we must disable _ARCH explicitly because
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# CONFIG_XTENSA turns it on (due to an xcc lack of gcc builtins?)
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#
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config ATOMIC_OPERATIONS_C
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default y
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config ATOMIC_OPERATIONS_ARCH
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default n
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config GEN_ISR_TABLES
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default y
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config GEN_SW_ISR_TABLE
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default y
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config GEN_IRQ_VECTOR_TABLE
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default n
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endif # SOC_FAMILY_MTK_ADSP
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