# Copyright 2023 The ChromiumOS Authors
# SPDX-License-Identifier: Apache-2.0

orsource "*/Kconfig.defconfig"

if SOC_FAMILY_MTK_ADSP

config INTC_MTK_ADSP
	default y

config XTENSA_SMALL_VECTOR_TABLE_ENTRY
	default y

config XTENSA_USE_CORE_CRT1
	default n

config MULTI_LEVEL_INTERRUPTS
	default y
config 2ND_LEVEL_INTERRUPTS
	default y
config MAX_IRQ_PER_AGGREGATOR
	default 32
config 2ND_LVL_ISR_TBL_OFFSET
	default 32

config MTK_ADSP_TIMER
	default y
config XTENSA_TIMER
	default n

config MAIN_STACK_SIZE
	default 2048

# This platform has a single big DRAM region where most linkage
# happens.  The libc heap normally wants to steal all of it, when in
# fact SOF has its own heap.  Just leave a little for stray malloc()
# calls to find.
config COMMON_LIBC_MALLOC_ARENA_SIZE
	default 32768

# Don't build the HAL if the toolchain already includes it.  Note that
# this is done in the SOC layer historically, really this belongs in
# arch/xtensa or the toolchain integration.
#
config XTENSA_HAL
	default n if "$(ZEPHYR_TOOLCHAIN_VARIANT)" = "xcc"
	default n if "$(ZEPHYR_TOOLCHAIN_VARIANT)" = "xt-clang"
	default y

config SOC_TOOLCHAIN_NAME
	default "mtk_mt8195_adsp"

config XTENSA_RESET_VECTOR
	default n

# This single-core device doesn't have S32C1I and so has no built-in
# atomics.  Note we must disable _ARCH explicitly because
# CONFIG_XTENSA turns it on (due to an xcc lack of gcc builtins?)
#
config ATOMIC_OPERATIONS_C
	default y
config ATOMIC_OPERATIONS_ARCH
	default n

config GEN_ISR_TABLES
	default y
config GEN_SW_ISR_TABLE
	default y
config GEN_IRQ_VECTOR_TABLE
	default n

endif # SOC_FAMILY_MTK_ADSP