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zephyr/dts/arc/synopsys/arc_hsdk.dtsi

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boards: hsdk: add initial support of ARC HS Development Kit This commit includes the initial support of ARC HS Development Kit: * hsdk soc support * hsdk board support * no mmu support, so no userspace * smp support Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
2019-07-25 16:44:41 +08:00
/*
* Copyright (c) 2019, Synopsys, Inc. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "skeleton.dtsi"
dts: migrate includes to <zephyr/...> In order to bring consistency in-tree, migrate all dts code to the new prefix <zephyr/...>. Note that the conversion has been scripted, refer to zephyrproject-rtos#45388 for more details. Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-05-06 17:02:05 +08:00
#include <zephyr/dt-bindings/i2c/i2c.h>
#include <zephyr/dt-bindings/gpio/gpio.h>
boards: hsdk: add initial support of ARC HS Development Kit This commit includes the initial support of ARC HS Development Kit: * hsdk soc support * hsdk board support * no mmu support, so no userspace * smp support Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
2019-07-25 16:44:41 +08:00
/ {
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "snps,archs38";
reg = <0>;
};
cpu@1 {
device_type = "cpu";
compatible = "snps,archs38";
reg = <1>;
};
cpu@2 {
device_type = "cpu";
compatible = "snps,archs38";
reg = <2>;
};
cpu@3 {
device_type = "cpu";
compatible = "snps,archs38";
reg = <3>;
};
};
intc: arcv2-intc {
compatible = "snps,arcv2-intc";
interrupt-controller;
#interrupt-cells = <2>;
};
idu_intc: idu-interrupt-controller {
compatible = "snps,archs-idu-intc";
interrupt-controller;
#interrupt-cells = <2>;
interrupt-parent = <&intc>;
};
soc: arc: define ICI in DT ICI (Inter-Core Interrupt Unit) interrupts and priorities were hardcoded in C files. This patch moves this information to Devicetree and updates code to make use of it. Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-06-15 22:34:01 +08:00
ici: intercore-interrupt-unit {
compatible = "snps,archs-ici";
interrupts = <19 1>;
interrupt-parent = <&intc>;
};
soc: arch: synopsys: move timer0/1 IRQ information to DT timer0/1 IRQ information was hardcoded in soc.h, however, Devicetree is nowadays a better place to describe hardware. Note that I have followed existing upstream Linux code to do these changes. Ref. - https://elixir.bootlin.com/linux/latest/source/arch/arc/boot/dts/ hsdk.dts - https://elixir.bootlin.com/linux/latest/source/Documentation/ devicetree/bindings/timer/snps,arc-timer.txt Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-06-15 19:14:40 +08:00
timer0: timer0 {
compatible = "snps,arc-timer";
interrupts = <16 1>;
interrupt-parent = <&intc>;
};
timer1: timer1 {
compatible = "snps,arc-timer";
interrupts = <17 1>;
interrupt-parent = <&intc>;
};
boards: hsdk: add initial support of ARC HS Development Kit This commit includes the initial support of ARC HS Development Kit: * hsdk soc support * hsdk board support * no mmu support, so no userspace * smp support Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
2019-07-25 16:44:41 +08:00
soc {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
interrupt-parent = <&idu_intc>;
ranges;
arc: hsdk: Set SRAM_BASE_ADDRESS in defconfig On power-on boot-ROM is mapped to address 0 in HSDK board. Normally later when U-Boot gets started by boot-ROM we change mappings so that real DDR is mapped to entire address space including 0: https://elixir.bootlin.com/u-boot/latest/source/board/synopsys/hsdk/hsdk.c#L474 But if U-Boot is not started (which is controlled by the BIM dip-switch on the board) boot-ROM remains mapped to 0, and essentially any attempt to write to that location fails, thus we cannot upload contents of our target Elf there even with JTAG. The next logical option is to use beginning of the non-translated memory region 0x8000_0000 which we typically use for loading U-Boot & Linux kernel on ARC boards. But in case of HSDK we have DCCM (Data Closely-Coupled MEmory - fast on-chip SRAM) mapped there and since we cannot execute code from DCCM we need to skip that region as well which gives us the next option being 0x9000_0000 . That's because DCCM owns entire 256 MiB "aperture" even though it may have much smaller size up-to 8 MiB. We are mapping only 5 apertures because the last two (0xe000_0000-0xffff_ffff) are used for peripherals and AXI. Signed-off-by: Evgeniy Didin <didin@synopsys.com> Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2019-11-12 16:00:51 +08:00
ddr0: memory@90000000 {
boards: hsdk: add initial support of ARC HS Development Kit This commit includes the initial support of ARC HS Development Kit: * hsdk soc support * hsdk board support * no mmu support, so no userspace * smp support Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
2019-07-25 16:44:41 +08:00
device_type = "memory";
arc: hsdk: Set SRAM_BASE_ADDRESS in defconfig On power-on boot-ROM is mapped to address 0 in HSDK board. Normally later when U-Boot gets started by boot-ROM we change mappings so that real DDR is mapped to entire address space including 0: https://elixir.bootlin.com/u-boot/latest/source/board/synopsys/hsdk/hsdk.c#L474 But if U-Boot is not started (which is controlled by the BIM dip-switch on the board) boot-ROM remains mapped to 0, and essentially any attempt to write to that location fails, thus we cannot upload contents of our target Elf there even with JTAG. The next logical option is to use beginning of the non-translated memory region 0x8000_0000 which we typically use for loading U-Boot & Linux kernel on ARC boards. But in case of HSDK we have DCCM (Data Closely-Coupled MEmory - fast on-chip SRAM) mapped there and since we cannot execute code from DCCM we need to skip that region as well which gives us the next option being 0x9000_0000 . That's because DCCM owns entire 256 MiB "aperture" even though it may have much smaller size up-to 8 MiB. We are mapping only 5 apertures because the last two (0xe000_0000-0xffff_ffff) are used for peripherals and AXI. Signed-off-by: Evgeniy Didin <didin@synopsys.com> Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2019-11-12 16:00:51 +08:00
reg = <0x90000000 0x50000000>;
boards: hsdk: add initial support of ARC HS Development Kit This commit includes the initial support of ARC HS Development Kit: * hsdk soc support * hsdk board support * no mmu support, so no userspace * smp support Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
2019-07-25 16:44:41 +08:00
};
uart0: uart@f0005000 {
compatible = "ns16550";
clock-frequency = <33333333>;
reg = <0xf0005000 0x1000>;
interrupts = <30 1>;
dts: add reg-shift property to all ns16550 devices The ns16550 flags reg-shift property as optional. In case it is not supplied, the ns16550 driver relies on a value defined in <soc.h>, or, by default it takes 4 (shift by 2). This patch adds the property to all ns16550 nodes, with the following values: - 2 if SoC did not have any custom value defined by UART_REG_ADDR_INTERVAL (corresponds to 1 << 2 = 4) - If SoC defined DEFAULT_REG_INTERVAL (snps_arc_iot/it8xxx2), use such value (4=2, 2=1, 1=0). These changes will allow simplifying the ns16550 driver. Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-06-15 19:59:22 +08:00
reg-shift = <2>;
boards: hsdk: add initial support of ARC HS Development Kit This commit includes the initial support of ARC HS Development Kit: * hsdk soc support * hsdk board support * no mmu support, so no userspace * smp support Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
2019-07-25 16:44:41 +08:00
};
uart1: uart@f0026000{
compatible = "ns16550";
clock-frequency = <33333333>;
reg = <0xf0026000 0x1000>;
interrupts = <46 1>;
dts: add reg-shift property to all ns16550 devices The ns16550 flags reg-shift property as optional. In case it is not supplied, the ns16550 driver relies on a value defined in <soc.h>, or, by default it takes 4 (shift by 2). This patch adds the property to all ns16550 nodes, with the following values: - 2 if SoC did not have any custom value defined by UART_REG_ADDR_INTERVAL (corresponds to 1 << 2 = 4) - If SoC defined DEFAULT_REG_INTERVAL (snps_arc_iot/it8xxx2), use such value (4=2, 2=1, 1=0). These changes will allow simplifying the ns16550 driver. Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-06-15 19:59:22 +08:00
reg-shift = <2>;
boards: hsdk: add initial support of ARC HS Development Kit This commit includes the initial support of ARC HS Development Kit: * hsdk soc support * hsdk board support * no mmu support, so no userspace * smp support Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
2019-07-25 16:44:41 +08:00
status = "disabled";
};
uart2: uart@f0027000 {
compatible = "ns16550";
clock-frequency = <33333333>;
reg = <0xf0027000 0x1000>;
interrupts = <47 1>;
dts: add reg-shift property to all ns16550 devices The ns16550 flags reg-shift property as optional. In case it is not supplied, the ns16550 driver relies on a value defined in <soc.h>, or, by default it takes 4 (shift by 2). This patch adds the property to all ns16550 nodes, with the following values: - 2 if SoC did not have any custom value defined by UART_REG_ADDR_INTERVAL (corresponds to 1 << 2 = 4) - If SoC defined DEFAULT_REG_INTERVAL (snps_arc_iot/it8xxx2), use such value (4=2, 2=1, 1=0). These changes will allow simplifying the ns16550 driver. Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-06-15 19:59:22 +08:00
reg-shift = <2>;
boards: hsdk: add initial support of ARC HS Development Kit This commit includes the initial support of ARC HS Development Kit: * hsdk soc support * hsdk board support * no mmu support, so no userspace * smp support Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
2019-07-25 16:44:41 +08:00
status = "disabled";
};
uart3: uart@f0028000 {
compatible = "ns16550";
clock-frequency = <33333333>;
reg = <0xf0028000 0x1000>;
interrupts = <48 1>;
dts: add reg-shift property to all ns16550 devices The ns16550 flags reg-shift property as optional. In case it is not supplied, the ns16550 driver relies on a value defined in <soc.h>, or, by default it takes 4 (shift by 2). This patch adds the property to all ns16550 nodes, with the following values: - 2 if SoC did not have any custom value defined by UART_REG_ADDR_INTERVAL (corresponds to 1 << 2 = 4) - If SoC defined DEFAULT_REG_INTERVAL (snps_arc_iot/it8xxx2), use such value (4=2, 2=1, 1=0). These changes will allow simplifying the ns16550 driver. Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-06-15 19:59:22 +08:00
reg-shift = <2>;
boards: hsdk: add initial support of ARC HS Development Kit This commit includes the initial support of ARC HS Development Kit: * hsdk soc support * hsdk board support * no mmu support, so no userspace * smp support Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
2019-07-25 16:44:41 +08:00
status = "disabled";
};
gpio0: gpio@f0003000 {
compatible = "snps,designware-gpio";
reg = <0xf0003000 0x1000>;
dts: designware-gpio: remove reduplicative property bits bits property indicates the number of in-use slots of available slots for GPIOS. We have a similar property ngpios in gpio-controller.yaml, we will use ngpios to calculate port_pin_mask. Let's remove bits and only use ngpios. Signed-off-by: Watson Zeng <zhiwei@synopsys.com>
2021-06-28 14:19:46 +08:00
ngpios = <24>;
boards: hsdk: add initial support of ARC HS Development Kit This commit includes the initial support of ARC HS Development Kit: * hsdk soc support * hsdk board support * no mmu support, so no userspace * smp support Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
2019-07-25 16:44:41 +08:00
interrupt-parent = <&idu_intc>;
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
boards: arc: hsdk: add creg_gpio driver support Add creg_gpio driver support for hsdk board. Signed-off-by: Watson Zeng <zhiwei@synopsys.com>
2021-06-29 14:57:46 +08:00
creg_gpio: creg_gpio@f00014b0 {
compatible = "snps,creg-gpio";
reg = <0xf00014b0 0x4>;
ngpios = <12>;
bit_per_gpio = <2>;
off_val = <0>;
on_val = <2>;
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
boards: hsdk: add initial support of ARC HS Development Kit This commit includes the initial support of ARC HS Development Kit: * hsdk soc support * hsdk board support * no mmu support, so no userspace * smp support Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
2019-07-25 16:44:41 +08:00
i2c0: i2c@f0023000 {
compatible = "snps,designware-i2c";
clock-frequency = <I2C_BITRATE_STANDARD>;
#address-cells = <1>;
#size-cells = <0>;
reg = <0xf0023000 0x1000>;
interrupts = <43 1>;
status = "disabled";
};
i2c1: i2c@f0024000 {
compatible = "snps,designware-i2c";
clock-frequency = <I2C_BITRATE_STANDARD>;
#address-cells = <1>;
#size-cells = <0>;
reg = <0xf0024000 0x1000>;
interrupts = <44 1>;
status = "disabled";
};
i2c2: i2c@f0025000 {
compatible = "snps,designware-i2c";
clock-frequency = <I2C_BITRATE_STANDARD>;
#address-cells = <1>;
#size-cells = <0>;
reg = <0xf0025000 0x1000>;
interrupts = <45 1>;
status = "disabled";
};
spi0: spi@f0020000 {
compatible = "snps,designware-spi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0xf0020000 0x1000>;
interrupts = <40 1>;
drivers: spi: add Data Fusion Subsystem SPI driver Introduce DesignWare ARC Data Fusion IP Subsystem(DFSS) SPI driver for ARC boards, i.e. EMSDP, which uses DW SPI to controll SPI-Flash and DFSS SPI to connect external devices. Both drivers share most source code, but DFSS uses ARC auxiliary registers. Move FIFO depth setting to device tree. Signed-off-by: Siyuan Cheng <siyuanc@synopsys.com>
2023-04-24 16:30:35 +08:00
fifo-depth = <32>;
drivers: spi: dw: define max-xfer-size The max size was determined by looking at the ARCH of the cpu. This really comes from the ip configuration when generated. Add `max-xfer-size` property to the devicetree. Signed-off-by: Ryan McClelland <ryanmcclelland@meta.com>
2023-11-10 07:27:21 +08:00
max-xfer-size = <16>;
boards: hsdk: add initial support of ARC HS Development Kit This commit includes the initial support of ARC HS Development Kit: * hsdk soc support * hsdk board support * no mmu support, so no userspace * smp support Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
2019-07-25 16:44:41 +08:00
status = "disabled";
};
spi1: spi@f0021000 {
compatible = "snps,designware-spi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0xf0021000 0x1000>;
interrupts = <41 1>;
drivers: spi: add Data Fusion Subsystem SPI driver Introduce DesignWare ARC Data Fusion IP Subsystem(DFSS) SPI driver for ARC boards, i.e. EMSDP, which uses DW SPI to controll SPI-Flash and DFSS SPI to connect external devices. Both drivers share most source code, but DFSS uses ARC auxiliary registers. Move FIFO depth setting to device tree. Signed-off-by: Siyuan Cheng <siyuanc@synopsys.com>
2023-04-24 16:30:35 +08:00
fifo-depth = <32>;
drivers: spi: dw: define max-xfer-size The max size was determined by looking at the ARCH of the cpu. This really comes from the ip configuration when generated. Add `max-xfer-size` property to the devicetree. Signed-off-by: Ryan McClelland <ryanmcclelland@meta.com>
2023-11-10 07:27:21 +08:00
max-xfer-size = <16>;
boards: hsdk: add initial support of ARC HS Development Kit This commit includes the initial support of ARC HS Development Kit: * hsdk soc support * hsdk board support * no mmu support, so no userspace * smp support Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
2019-07-25 16:44:41 +08:00
status = "disabled";
};
spi2: spi@f0022000 {
compatible = "snps,designware-spi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0xf0022000 0x1000>;
interrupts = <42 1>;
drivers: spi: add Data Fusion Subsystem SPI driver Introduce DesignWare ARC Data Fusion IP Subsystem(DFSS) SPI driver for ARC boards, i.e. EMSDP, which uses DW SPI to controll SPI-Flash and DFSS SPI to connect external devices. Both drivers share most source code, but DFSS uses ARC auxiliary registers. Move FIFO depth setting to device tree. Signed-off-by: Siyuan Cheng <siyuanc@synopsys.com>
2023-04-24 16:30:35 +08:00
fifo-depth = <32>;
drivers: spi: dw: define max-xfer-size The max size was determined by looking at the ARCH of the cpu. This really comes from the ip configuration when generated. Add `max-xfer-size` property to the devicetree. Signed-off-by: Ryan McClelland <ryanmcclelland@meta.com>
2023-11-10 07:27:21 +08:00
max-xfer-size = <16>;
boards: hsdk: add initial support of ARC HS Development Kit This commit includes the initial support of ARC HS Development Kit: * hsdk soc support * hsdk board support * no mmu support, so no userspace * smp support Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
2019-07-25 16:44:41 +08:00
status = "disabled";
};
};
arc: hsdk: Set SRAM_BASE_ADDRESS in defconfig On power-on boot-ROM is mapped to address 0 in HSDK board. Normally later when U-Boot gets started by boot-ROM we change mappings so that real DDR is mapped to entire address space including 0: https://elixir.bootlin.com/u-boot/latest/source/board/synopsys/hsdk/hsdk.c#L474 But if U-Boot is not started (which is controlled by the BIM dip-switch on the board) boot-ROM remains mapped to 0, and essentially any attempt to write to that location fails, thus we cannot upload contents of our target Elf there even with JTAG. The next logical option is to use beginning of the non-translated memory region 0x8000_0000 which we typically use for loading U-Boot & Linux kernel on ARC boards. But in case of HSDK we have DCCM (Data Closely-Coupled MEmory - fast on-chip SRAM) mapped there and since we cannot execute code from DCCM we need to skip that region as well which gives us the next option being 0x9000_0000 . That's because DCCM owns entire 256 MiB "aperture" even though it may have much smaller size up-to 8 MiB. We are mapping only 5 apertures because the last two (0xe000_0000-0xffff_ffff) are used for peripherals and AXI. Signed-off-by: Evgeniy Didin <didin@synopsys.com> Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2019-11-12 16:00:51 +08:00
};